Patent Application
20240123561
This disclosure generally relates to systems and methods for wafer and panel processing and, more particularly, to magnet-driven chemical-mechanical polishing.
Wafer and panel processing require planarization, which is the process of polishing of the surface using an abrasive and/or reactive slurry. This slurry needs to be moved around the face of the wafer/panel.
Certain implementations will now be described more fully below with reference to the accompanying drawings, in which various implementations and/or aspects are shown. However, various aspects may be implemented in many different forms and should not be construed as limited to the implementations set forth herein; rather, these implementations are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art. Like numbers in the figures refer to like elements throughout. Hence, if a feature is used across several drawings, the number used to identify the feature in the drawing where the feature first appeared will be used in later drawings.
The following description and the drawings sufficiently illustrate specific embodiments to enable those skilled in the art to practice them. Other embodiments may incorporate structural, logical, electrical, process, algorithm, and other changes. Portions and features of some embodiments may be included in, or substituted for, those of other embodiments. Embodiments set forth in the claims encompass all available equivalents of those claims.
Wafer and panel processing require planarization, which is the polishing of the surface using an abrasive and/or reactive slurry. This slurry needs to be moved around the face of the wafer/panel. In such an application, a rough pad is used to move the slurry around and apply pressure to the slurry. Both pad and wafer/panel are rotated to ensure uniform polishing. This leads to the pad wearing out resulting in a need to condition, re-rough, and eventually replace the pad. Further, the pad and the wafer/panel must both be rotated, which is difficult for fragile wafers/panels (e.g., thin glass/silicon). Furthermore, it is hard to fine-tune polishing rates on different parts of the wafer/panel. Therefore, there is a need for a non-mechanical process that does not rotate the pad and/or the wafer but still provides a polished wafer.
Example embodiments of the present disclosure relate to systems, methods, and devices for Magnet-driven Chemical-Mechanical Polishing.
In one or more embodiments, an enhanced plate polishing system may use an array(s) of electromagnets to create time-varying magnetic fields in the ferrofluid slurry, moving the slurry without the need for moving the pad/wafer/panel. The enhanced plate polishing system may apply pressure with an immobile pad, and chuck the panel/wafer in place.
In one or more embodiments, an enhanced plate polishing system may, instead of using a mechanical process of having a pad that rotates (that results in wearing out), dope or infuse the slurry with magnetic particles or magnetic coatings on the slurry, and then use magnetic fields to move all the slurry around and get a similar effect as rotation and movement without using the pad.
In one or more embodiments, an enhanced plate polishing system may provide: 1) a decreased cost of ownership (no pad replacement); 2) increased throughput (no pad conditioning); 3) enable handling of fragile wafers/panels; 4) finer control of polishing rates (each electromagnet is controlled independently); and/or 5) less exclusion area on the edge of the wafers/panels (due to lack of pad).
The above descriptions are for purposes of illustration and are not meant to be limiting. Numerous other examples, configurations, processes, algorithms, etc., may exist, some of which are described in greater detail below. Example embodiments will now be described with reference to the accompanying figures.
Referring to
In some examples, assuming that the wire is 14-gauge, the iron cores are 1 cm diameter, 7 mm height (unimportant), and the current per wire is 10 A. These numbers can be varied. Optionally, a similar array of coils can be placed above the plate.
In one or more embodiments, the slurry flows from above the plate to below the plate, with an estimated gap of about 1 cm. This slurry contains both ferrofluidic components (estimated magnetization at saturation, 104 kA/m) and chemical mechanical polishing (CMP) components (abrasives and/or chemicals), either suspended in the same fluid or with ferromagnetic components attached to the abrasive/components.
In one or more embodiments, the current through the coils can be manipulated so that there is a strong gradient in the magnetic field between the centers of two adjacent coils, one with a “positive” current and the other with a “negative” current. This gradient can cause an acceleration in the fluid, causing the slurry to have enough speed relative to the panel to planarize it, without moving any solid parts. The patterns of currents can be varied so that the fluid flows in a fast, pseudorandom (or controlled) pattern, planarizing the entire panel as desired. Eventually, the fluid escapes off the sides.
Any magnetic parts can be easily separated and recycled. Support modules (located either in the subfab or adjacent to the tool) may be used to re-qualify used ferrofluids by separating the magnetic particles from the fluid. Stratification of the magnetic particles may then be performed (again by applying magnetic fields within a viscous medium) to remove the smallest particles along with the effluent waste. Then, the fluid component of the ferrofluid may be mixed with the remaining particles to reconstitute the slurry for reuse.
Furthermore, the coils can be attached to a frame that rocks ˜3 mm in all 4 directions, so that each part of the panel spends equal time under the center of its coil (versus the edge). This will improve uniformity. It should be understood that lengths may be scaled up or down with similar effects.
Typically, magnetic fields have a peak when (1−α)2+β2 is minimized, where a is the radial distance divided by the loop radius, and β is the axial distance divided by the loop radius.
Since this is the sum of two squares, the minimum is at α˜1 and β→0, which requires a loop radius much larger than the “panel” thickness. In one or more embodiments, an enhanced plate polishing system may have an electromagnet as an iron core, which is assumed to have a susceptibility of 1000 (conservative estimate; can be 1-2 orders of magnitude higher). The heat loss of a 10 A current is approximately 0.15 W/coil, or about 400 W for the entire array.
Referring to
An enhanced plate polishing system may utilize one or more pairs of coils with an opposite current to double the effect.
It is known that the behavior of a fluid in a magnetic field is governed by:
The last two terms may be neglected, and, since the field is varying in time quickly enough to avoid a pressure buildup, the first term of the RHS may also be ignored. Thus, noting that radially,
for a pair of opposite-current coils, over 2 cm (from the center of one coil to the center of the next), and that M˜104 for a typical ferrofluid,
with a typical density near that of water.
Newton's equations of motion state that by the center of the second coil, the velocity of the fluid will be
which is about 3× POR. Note that in POR, the velocity is measured between pad and panel, while here, it is measured between panel and the nearest liquid, further enhancing this method's advantage.
Furthermore, compare the magnetic-related acceleration (400 m/s2) to the acceleration due to the pressure gradient,
Thus, the magnetic acceleration is sufficient to redirect the fluid as necessary.
It is understood that the above descriptions are for purposes of illustration and are not meant to be limiting.
At block 302, a device (e.g., the enhanced plate polishing device of
At block 304, the device may utilize a controller to vary a current flowing through an array of coils. Varying the current with the controller may cause a magnetic field within the ferrofluid or the mixture of the ferrofluid with the chemical. The magnetic field causes the ferrofluid to polish a first surface of the panel. The controller turns each coil of the array of coils to be on or off based on a pattern.
At block 306, the device may apply pressure on the plate to press against the liquid and the wafer. The array of coils or the panel sits above a springloaded frame, wherein the springloaded frame is configured to move laterally to vary a location of the magnetic field.
It is understood that the above descriptions are for purposes of illustration and are not meant to be limiting.
In various embodiments, the computing system 400 may comprise or be implemented as part of an electronic device.
In some embodiments, the computing system 400 may be representative, for example, of a computer system that implements one or more components of
The embodiments are not limited in this context. More generally, the computing system 400 is configured to implement all logic, systems, processes, logic flows, methods, equations, apparatuses, and functionality described herein and with reference to
The system 400 may be a computer system with multiple processor cores such as a distributed computing system, supercomputer, high-performance computing system, computing cluster, mainframe computer, mini-computer, client-server system, personal computer (PC), workstation, server, portable computer, laptop computer, tablet computer, a handheld device such as a personal digital assistant (PDA), or other devices for processing, displaying, or transmitting information. Similar embodiments may comprise, e.g., entertainment devices such as a portable music player or a portable video player, a smart phone or other cellular phones, a telephone, a digital video camera, a digital still camera, an external storage device, or the like. Further embodiments implement larger scale server configurations. In other embodiments, the system 400 may have a single processor with one core or more than one processor. Note that the term “processor” refers to a processor with a single core or a processor package with multiple processor cores.
In at least one embodiment, the computing system 400 is representative of one or more components of
As used in this application, the terms “system” and “component” and “module” are intended to refer to a computer-related entity, either hardware, a combination of hardware and software, software, or software in execution, examples of which are provided by the exemplary system 400. For example, a component can be, but is not limited to being, a process running on a processor, a processor, a hard disk drive, multiple storage drives (of optical and/or magnetic storage medium), an object, an executable, a thread of execution, a program, and/or a computer.
By way of illustration, both an application running on a server and the server can be a component. One or more components can reside within a process and/or thread of execution, and a component can be localized on one computer and/or distributed between two or more computers. Further, components may be communicatively coupled to each other by various types of communications media to coordinate operations. The coordination may involve the uni-directional or bi-directional exchange of information. For instance, the components may communicate information in the form of signals communicated over the communications media. The information can be implemented as signals allocated to various signal lines. In such allocations, each message is a signal. Further embodiments, however, may alternatively employ data messages. Such data messages may be sent across various connections. Exemplary connections include parallel interfaces, serial interfaces, and bus interfaces.
As shown in this figure, system 400 comprises a motherboard 405 for mounting platform components. The motherboard 405 is a point-to-point interconnect platform that includes a processor 410, a processor 430 coupled via a point-to-point interconnects as an Ultra Path Interconnect (UPI), and an enhanced plate polishing device 419. In other embodiments, the system 400 may be of another bus architecture, such as a multi-drop bus. Furthermore, each of processors 410 and 430 may be processor packages with multiple processor cores. As an example, processors 410 and 430 are shown to include processor core(s) 420 and 440, respectively. While the system 400 is an example of a two-socket (2S) platform, other embodiments may include more than two sockets or one socket. For example, some embodiments may include a four-socket (4S) platform or an eight-socket (8S) platform. Each socket is a mount for a processor and may have a socket identifier. Note that the term platform refers to the motherboard with certain components mounted such as the processors 410 and the chipset 460. Some platforms may include additional components and some platforms may only include sockets to mount the processors and/or the chipset.
The processors 410 and 430 can be any of various commercially available processors, including without limitation an Intel® Celeron®, Core®, Core (2) Duo®, Itanium®, Pentium®, Xeon®, and XScale® processors; AMD® Athlon®, Duron® and Opteron® processors; ARM® application, embedded and secure processors; IBM® and Motorola® DragonBall® and PowerPC® processors; IBM and Sony® Cell processors; and similar processors. Dual microprocessors, multi-core processors, and other multi-processor architectures may also be employed as the processors 410, and 430.
The processor 410 includes an integrated memory controller (IMC) 414, registers 416, and point-to-point (P-P) interfaces 418 and 452. Similarly, the processor 430 includes an IMC 434, registers 436, and P-P interfaces 438 and 454. The IMC's 414 and 434 couple the processors 410 and 430, respectively, to respective memories, a memory 412 and a memory 432. The memories 412 and 432 may be portions of the main memory (e.g., a dynamic random-access memory (DRAM)) for the platform such as double data rate type 3 (DDR3) or type 4 (DDR4) synchronous DRAM (SDRAM). In the present embodiment, the memories 412 and 432 locally attach to the respective processors 410 and 430.
In addition to the processors 410 and 430, the system 400 may include an enhanced plate polishing device 419. The enhanced plate polishing device 419 may be connected to chipset 460 by means of P-P interfaces 429 and 469. The enhanced plate polishing device 419 may also be connected to a memory 439. In some embodiments, the enhanced plate polishing device 419 may be connected to at least one of the processors 410 and 430. In other embodiments, the memories 412, 432, and 439 may couple with the processor 410 and 430, and the enhanced plate polishing device 419 via a bus and shared memory hub.
System 400 includes chipset 460 coupled to processors 410 and 430. Furthermore, chipset 460 can be coupled to storage medium 403, for example, via an interface (I/F) 466. The I/F 466 may be, for example, a Peripheral Component Interconnect-enhanced (PCI-e). The processors 410, 430, and the enhanced plate polishing device 419 may access the storage medium 403 through chipset 460.
Storage medium 403 may comprise any non-transitory computer-readable storage medium or machine-readable storage medium, such as an optical, magnetic or semiconductor storage medium. In various embodiments, storage medium 403 may comprise an article of manufacture. In some embodiments, storage medium 403 may store computer-executable instructions, such as computer-executable instructions 402 to implement one or more of processes or operations described herein, (e.g., process 300 of
The processor 410 couples to a chipset 460 via P-P interfaces 452 and 462 and the processor 430 couples to a chipset 460 via P-P interfaces 454 and 464. Direct Media Interfaces (DMIs) may couple the P-P interfaces 452 and 462 and the P-P interfaces 454 and 464, respectively. The DMI may be a high-speed interconnect that facilitates, e.g., eight Giga Transfers per second (GT/s) such as DMI 3.0. In other embodiments, the processors 410 and 430 may interconnect via a bus.
The chipset 460 may comprise a controller hub such as a platform controller hub (PCH). The chipset 460 may include a system clock to perform clocking functions and include interfaces for an I/O bus such as a universal serial bus (USB), peripheral component interconnects (PCIs), serial peripheral interconnects (SPIs), integrated interconnects (I2Cs), and the like, to facilitate connection of peripheral devices on the platform. In other embodiments, the chipset 460 may comprise more than one controller hub such as a chipset with a memory controller hub, a graphics controller hub, and an input/output (I/O) controller hub.
In the present embodiment, the chipset 460 couples with a trusted platform module (TPM) 472 and the UEFI, BIOS, Flash component 474 via an interface (I/F) 470. The TPM 472 is a dedicated microcontroller designed to secure hardware by integrating cryptographic keys into devices. The UEFI, BIOS, Flash component 474 may provide pre-boot code.
Furthermore, chipset 460 includes the I/F 466 to couple chipset 460 with a high-performance graphics engine, graphics card 465. In other embodiments, the system 400 may include a flexible display interface (FDI) between the processors 410 and 430 and the chipset 460. The FDI interconnects a graphics processor core in a processor with the chipset 460.
Various I/O devices 492 couple to the bus 481, along with a bus bridge 480 which couples the bus 481 to a second bus 491 and an I/F 468 that connects the bus 481 with the chipset 460. In one embodiment, the second bus 491 may be a low pin count (LPC) bus. Various devices may couple to the second bus 491 including, for example, a keyboard 482, a mouse 484, communication devices 486, a storage medium 401, and an audio I/O 490.
The artificial intelligence (AI) accelerator 467 may be circuitry arranged to perform computations related to AI. The AI accelerator 467 may be connected to storage medium 403 and chipset 460. The AI accelerator 467 may deliver the processing power and energy efficiency needed to enable abundant-data computing. The AI accelerator 467 is a class of specialized hardware accelerators or computer systems designed to accelerate artificial intelligence and machine learning applications, including artificial neural networks and machine vision. The AI accelerator 467 may be applicable to algorithms for robotics, internet of things, other data-intensive and/or sensor-driven tasks.
Many of the I/O devices 492, communication devices 486, and the storage medium 401 may reside on the motherboard 405 while the keyboard 482 and the mouse 484 may be add-on peripherals. In other embodiments, some or all the I/O devices 492, communication devices 486, and the storage medium 401 are add-on peripherals and do not reside on the motherboard 405.
Some examples may be described using the expression “in one example” or “an example” along with their derivatives. These terms mean that a particular feature, structure, or characteristic described in connection with the example is included in at least one example. The appearances of the phrase “in one example” in various places in the specification are not necessarily all referring to the same example.
Some examples may be described using the expression “coupled” and “connected” along with their derivatives. These terms are not necessarily intended as synonyms for each other. For example, descriptions using the terms “connected” and/or “coupled” may indicate that two or more elements are in direct physical or electrical contact with each other. The term “coupled,” however, may also mean that two or more elements are not in direct contact with each other, yet still co-operate or interact with each other.
In addition, in the foregoing Detailed Description, various features are grouped together in a single example to streamline the disclosure. This method of disclosure is not to be interpreted as reflecting an intention that the claimed examples require more features than are expressly recited in each claim. Rather, as the following claims reflect, the inventive subject matter lies in less than all features of a single disclosed example. Thus, the following claims are hereby incorporated into the Detailed Description, with each claim standing on its own as a separate example. In the appended claims, the terms “including” and “in which” are used as the plain-English equivalents of the respective terms “comprising” and “wherein,” respectively. Moreover, the terms “first,” “second,” “third,” and so forth, are used merely as labels and are not intended to impose numerical requirements on their objects.
Although the subject matter has been described in language specific to structural features and/or methodological acts, it is to be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or acts described above. Rather, the specific features and acts described above are disclosed as example forms of implementing the claims.
A data processing system suitable for storing and/or executing program code will include at least one processor coupled directly or indirectly to memory elements through a system bus. The memory elements can include local memory employed during actual execution of the program code, bulk storage, and cache memories which provide temporary storage of at least some program code to reduce the number of times code must be retrieved from bulk storage during execution. The term “code” covers a broad range of software components and constructs, including applications, drivers, processes, routines, methods, modules, firmware, microcode, and subprograms. Thus, the term “code” may be used to refer to any collection of instructions which, when executed by a processing system, perform a desired operation or operations.
Logic circuitry, devices, and interfaces herein described may perform functions implemented in hardware and implemented with code executed on one or more processors. Logic circuitry refers to the hardware or the hardware and code that implements one or more logical functions. Circuitry is hardware and may refer to one or more circuits. Each circuit may perform a particular function. A circuit of the circuitry may comprise discrete electrical components interconnected with one or more conductors, an integrated circuit, a chip package, a chipset, memory, or the like. Integrated circuits include circuits created on a substrate such as a silicon wafer and may comprise components. And integrated circuits, processor packages, chip packages, and chipsets may comprise one or more processors.
Processors may receive signals such as instructions and/or data at the input(s) and process the signals to generate the at least one output. While executing code, the code changes the physical states and characteristics of transistors that make up a processor pipeline. The physical states of the transistors translate into logical bits of ones and zeros stored in registers within the processor. The processor can transfer the physical states of the transistors into registers and transfer the physical states of the transistors to another storage medium.
A processor may comprise circuits to perform one or more sub-functions implemented to perform the overall function of the processor. One example of a processor is a state machine or an application-specific integrated circuit (ASIC) that includes at least one input and at least one output. A state machine may manipulate the at least one input to generate the at least one output by performing a predetermined series of serial and/or parallel manipulations or transformations on the at least one input.
The logic as described above may be part of the design for an integrated circuit chip. The chip design is created in a graphical computer programming language, and stored in a computer storage medium or data storage medium (such as a disk, tape, physical hard drive, or virtual hard drive such as in a storage access network). If the designer does not fabricate chips or the photolithographic masks used to fabricate chips, the designer transmits the resulting design by physical means (e.g., by providing a copy of the storage medium storing the design) or electronically (e.g., through the Internet) to such entities, directly or indirectly. The stored design is then converted into the appropriate format (e.g., GDSII) for the fabrication.
The resulting integrated circuit chips can be distributed by the fabricator in raw wafer form (that is, as a single wafer that has multiple unpackaged chips), as a bare die, or in a packaged form. In the latter case, the chip is mounted in a single chip package (such as a plastic carrier, with leads that are affixed to a motherboard or other higher-level carrier) or in a multichip package (such as a ceramic carrier that has either or both surface interconnections or buried interconnections). In any case, the chip is then integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either (a) an intermediate product, such as a processor board, a server platform, or a motherboard, or (b) an end product.
The word “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any embodiment described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments. The terms “computing device,” “user device,” “communication station,” “station,” “handheld device,” “mobile device,” “wireless device” and “user equipment” (UE) as used herein refers to a wireless communication device such as a cellular telephone, a smartphone, a tablet, a netbook, a wireless terminal, a laptop computer, a femtocell, a high data rate (HDR) subscriber station, an access point, a printer, a point of sale device, an access terminal, or other personal communication system (PCS) device. The device may be either mobile or stationary.
As used within this document, the term “communicate” is intended to include transmitting, or receiving, or both transmitting and receiving. This may be particularly useful in claims when describing the organization of data that is being transmitted by one device and received by another, but only the functionality of one of those devices is required to infringe the claim. Similarly, the bidirectional exchange of data between two devices (both devices transmit and receive during the exchange) may be described as “communicating,” when only the functionality of one of those devices is being claimed. The term “communicating” as used herein with respect to a wireless communication signal includes transmitting the wireless communication signal and/or receiving the wireless communication signal. For example, a wireless communication unit, which is capable of communicating a wireless communication signal, may include a wireless transmitter to transmit the wireless communication signal to at least one other wireless communication unit, and/or a wireless communication receiver to receive the wireless communication signal from at least one other wireless communication unit.
As used herein, unless otherwise specified, the use of the ordinal adjectives “first,” “second,” “third,” etc., to describe a common object, merely indicates that different instances of like objects are being referred to and are not intended to imply that the objects so described must be in a given sequence, either temporally, spatially, in ranking, or in any other manner.
Certain aspects of the disclosure are described above with reference to block and flow diagrams of systems, methods, apparatuses, and/or computer program products according to various implementations. It will be understood that one or more blocks of the block diagrams and flow diagrams, and combinations of blocks in the block diagrams and the flow diagrams, respectively, may be implemented by computer-executable program instructions. Likewise, some blocks of the block diagrams and flow diagrams may not necessarily need to be performed in the order presented, or may not necessarily need to be performed at all, according to some implementations.
These computer-executable program instructions may be loaded onto a special-purpose computer or other particular machine, a processor, or other programmable data processing apparatus to produce a particular machine, such that the instructions that execute on the computer, processor, or other programmable data processing apparatus create means for implementing one or more functions specified in the flow diagram block or blocks. These computer program instructions may also be stored in a computer-readable storage media or memory that may direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable storage media produce an article of manufacture including instruction means that implement one or more functions specified in the flow diagram block or blocks. As an example, certain implementations may provide for a computer program product, comprising a computer-readable storage medium having a computer-readable program code or program instructions implemented therein, said computer-readable program code adapted to be executed to implement one or more functions specified in the flow diagram block or blocks. The computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational elements or steps to be performed on the computer or other programmable apparatus to produce a computer-implemented process such that the instructions that execute on the computer or other programmable apparatus provide elements or steps for implementing the functions specified in the flow diagram block or blocks.
Accordingly, blocks of the block diagrams and flow diagrams support combinations of means for performing the specified functions, combinations of elements or steps for performing the specified functions and program instruction means for performing the specified functions. It will also be understood that each block of the block diagrams and flow diagrams, and combinations of blocks in the block diagrams and flow diagrams, may be implemented by special-purpose, hardware-based computer systems that perform the specified functions, elements or steps, or combinations of special-purpose hardware and computer instructions.
Conditional language, such as, among others, “can,” “could,” “might,” or “may,” unless specifically stated otherwise, or otherwise understood within the context as used, is generally intended to convey that certain implementations could include, while other implementations do not include, certain features, elements, and/or operations. Thus, such conditional language is not generally intended to imply that features, elements, and/or operations are in any way required for one or more implementations or that one or more implementations necessarily include logic for deciding, with or without user input or prompting, whether these features, elements, and/or operations are included or are to be performed in any particular implementation.
Many modifications and other implementations of the disclosure set forth herein will be apparent having the benefit of the teachings presented in the foregoing descriptions and the associated drawings. Therefore, it is to be understood that the disclosure is not to be limited to the specific implementations disclosed and that modifications and other implementations are intended to be included within the scope of the appended claims. Although specific terms are employed herein, they are used in a generic and descriptive sense only and not for purposes of limitation.
