Patent Application
20070242505
The magnetic memory device and the method for driving the same according to one embodiment of the present invention will be explained with reference to
First, the structure of the magnetic memory device according to the present embodiment will be explained with reference to FIGS. 1 and 2A-2B.
A device isolation film 12 for defining a device region is formed on a silicon substrate 10. The device region has a rectangular shape elongated in the X-direction.
On the silicon substrate 10 with the device isolation film 12 formed on, a word line WL is formed, extended in the Y-direction. In the device region on both sides of the word line WL, source/drain regions 16, 18 are formed. Thus, in the device region, a select transistor comprising the gate electrode 14 formed of the word line WL and the source/drain regions 16, 18 is formed.
On the silicon substrate 10 with the select transistor formed on, an inter-layer insulating film 20 is formed. In the inter-layer insulating film 20, a contact plug 24 connected to the source/drain region 16 is formed. On the inter-layer insulating film 20 with the contact plug 24 formed in, a source line 26 is formed, extended in the Y-direction and electrically connected to the source/drain region 16 via the contact plug 24.
On the inter-layer insulating film 20 with the source line 26 formed on, an inter-layer insulating film 28 is formed. On the inter-layer insulating film 28, a read bit line 30 is formed, extended in the X-direction.
On the inter-layer insulating film 28 with the read bit line 30 formed on, an inter-layer insulating film 32 is formed. In the inter-layer insulating film 32, a contact plug 36 connected to the read bit line 30 is formed. On the inter-layer insulating film 32 with the contact plug 36 formed in, a lower electrode layer 30 is formed, electrically connected to the read bit line 30 via the contact plug 36.
On the lower electrode layer 38, an anti-ferromagnetic layer 40, a pinned magnetization layer (a first magnetic layer) 42 and a barrier layer (a non-magnetic layer) 50 are formed. On the inter-layer insulating film 32 with the lower electrode layer 38, the anti-ferromagnetic layer 40 and the pinned magnetization layer 42 and the barrier layer 50 formed on, an inter-layer insulating film 44 is formed, burying the lower electrode layer 38, the anti-ferromagnetic layer 40 and the pinned magnetization layer 42 and the barrier layer 50 with the upper surface of the barrier layer 50 exposed. In the inter-layer insulating films 44, 32, 28, 20, a contact plug 48 connected to the source/drain region 18 is formed.
On the inter-layer insulating film 44, a free magnetization layer (a second magnetic layer) 52 is formed electrically connected to the source/drain region 18 via the contact plug 48 and opposed to the pinned magnetization layer 42 with the barrier layer 50 formed therebetween. Thus, a magnetoresistive effect element 54 comprising the anti-ferromagnetic layer 40, the pinned magnetization layer 42, the barrier layer 50 and the free magnetization layer 52 is formed. The magnetoresistive effect element 54 has the free magnetization layer 52 extended in the X-direction and the pinned magnetization layer 42 arranged at the center with the barrier layer 50 formed therebetween.
On the inter-layer insulating film 44 with the free magnetization layer 52 formed on, an inter-layer insulating film 56 is formed. In the inter-layer insulating film 56, a contact plug 60 connected to the free magnetization layer 52 is formed. On the inter-layer insulating film 56 with the contact plug 60 formed in, a write bit line 62 is formed, extended in the X-direction and electrically connected to the free magnetization layer 52 via the contact plug 60.
Thus, the spin injection magnetic memory device including a memory cell formed of one select transistor and one magnetoresistive effect element is formed.
In the magnetic memory device according to the present embodiment, as described above, the free magnetization layer 52 of the magnetoresistive effect element 54 is elongated in the X-direction, and write current can be flowed in plane along the direction of the length of the free magnetization direction 52. The pinned magnetization layer 42 is provided on the central part of the fee magnetization layer 52 of the magnetoresistive effect element 54 with the barrier layer 50 formed therebetween, so that read current can be flowed perpendicularly to plane.
Next, the operational principle of the magnetoresistive effect element 54 of the magnetic memory device according to the present embodiment will be explained with reference to
As shown in
It is assumed here that the magnetization directions of the magnetic domains of the free magnetization layer 52 are opposed to each other with respect to the magnetic domain wall 70. That is, in
In the state shown in
At this time, the magnetic domain wall 70 is shifted left or right beyond the region where the pinned magnetization wall 42 is formed, a magnetization direction of a part of the free magnetization layer 52, opposed to the pinned magnetization layer 42 with the barrier layer 50 therebetween is changed.
That is, as shown in
Thus, the shift of the magnetic domain wall by the electron spin injection is utilized to define two-valued states that the magnetization directions of the magnetoresistive effect element are parallel and anti-parallel.
However, in the free magnetization layer 52 simply formed in a fine line structure, the magnetic domain wall 70 continues to be shifted in the direction of the electron spins. To prevent this, the notches 72 are provided in the free magnetization layer 52 near both ends thereof. It is generally known that the thin line structure has a defect, such as a crack or a cut, the shift of the magnetic domain wall is pinned there. Then, the notches 72 called the magnetic domain wall pinning sites are provided in the free magnetization layer 52 near both ends, whereby the range of the shift of the magnetic domain wall 70 can be controlled, and the operational reliability of the writing can be improved.
The notches 72 are not essentially trapezoidal as shown and can provide the same effect in a wedge-shape, rectangular shape, semi-spherical shape or other shapes. The shape of the notches 72 can be freely selected corresponding to a device structure.
In the single ferromagnetic fine line, in which the magnetization is directed in the direction of the length of the fine line, and both ends of the fine line are magnetic poles, it is generally difficult that the magnetic domain wall takes place. However, when the fine line has irregular patterns, the magnetic domain walls tend to take place at the parts. For example, it has been confirmed that a 500 nm-rhombic pattern is formed at the end of a 240 nm-width fine line, and an external magnetic field is applied at 26 degrees to the extension of the fine line, whereby the magnetic domain wall can be induced in the fine line having no magnetic domain wall (e.g., see Reference 7). In the present embodiment as well, it is possible that such method is utilized to induce the magnetic domain wall in the free magnetization layer 52.
Then, the method for writing the magnetic memory device according to the present embodiment will be explained.
For the writing in the magnetic memory device shown in
When a prescribed drive voltage is applied to the word line WL, and the select transistor is turned on, a current path of the write bit line 62—the contact plug 60—the free magnetization layer 52—the contact plug 48—the select transistor—the source line 26 serially connected to each other is formed between the write bit line 62 and he source line 26. In this current path, the prescribed write current can be flowed in the in-plane direction of the free magnetization layer 52. Accordingly, the direction of the current flowed in the current path is suitably changed to thereby memory required information in the magnetoresistive effect element 54.
For example, the write current is flowed from the source line 26 toward the write bit line 62, whereby in the free magnetization layer 52, the magnetic domain wall 70 is shifted in the direction shown in
In the writing of the magnetoresistive effect element 54 utilizing the shift of the magnetic domain wall by the electron spin injection as described above, it is not necessary to flow the write current perpendicularly to plane, i.e., via the barrier layer 50. Accordingly, the barrier layer 50 is free from the degradation due to the writing, and the reliability, such as the device life, etc., can be improved.
In the magnetic memory device including a plurality of the magnetoresistive effect elements 54, when bit information of the magnetoresistive effect elements 54 is initialized at once, it is effective to apply a strong external magnetic field in one direction.
Then, the method for reading the magnetic memory device according to the present embodiment will be explained.
In the reading of the magnetic memory device shown in
When a prescribed drive voltage is applied to the word line WL, and the select transistor is turned on, the current path of the read bit line 30—the contact plug 36 the magnetoresistive effect element 54—the contact plug 48—the selection-transistor—the source line 26 serially connected to each other is formed between the read bit line 30 and the source line 26. In this current path, the read current can be flowed to the magnetoresistive effect element 54 perpendicularly to plane. Accordingly, the read current is flowed by this current path, and a voltage outputted to the read bit line 30 is detected, whereby the resistance state of the magnetoresistive effect element 54 can be judged.
Next, characteristics of the magnetic memory device according to the present embodiment will be proved.
First, the electric power consumption of the magnetoresistive effect element will be discussed.
When a real resistance (except the parasitic resistances of the circuit, etc.) of the magnetoresistive effect element RTMR is 5 kΩ, a device area S is 0.01 μm2, and a write voltage Vw is 500 mV, a write current Iw for the conventional MRAM, in which the write current is flowed perpendicularly to plane (hereinafter called CPP (Current Perpendicular to Plane) type MRAM), is
I
W
=V
W
/R
TMR=0.1 mA
W=V
W
×I
W=500 mV×0.1 mA=50 μW
On the other hand, in the MRAM, in which the write current is flowed in the in-plane direction of the free magnetization layer according to the present embodiment (hereinafter called a CIP (Current in In-Plane) type MRAM), when a sectional area S of the free magnetization layer 52 of NiFe is 240 nm×100 nm, a write current Iw is Iw=Jc×S=3.12 mA, a specific resistance ρFe of Fe is ρFe=1.0×10−7 Ω-cm, and a shift distance L of the magnetic domain wall is 1.5 μm, a real resistance R of the free magnetization layer is
W=I
2
×R(3.12 mA)2×0.628 Ω=6.1 μW
It is found that the present embodiment can decrease the electric power consumption by one place in comparison with that of the CPP-type MRAM. This is due to the fact that the tunnel resistance of the barrier layer is very high in the CPP-type MRAM, but in the CIP-type MRAM, wherein the electric conduction is in the metal, the resistance is very low.
Then, the output of the magnetoresistive effect element will be discussed.
As shown, it is found that when the MgO film thickness is about 1.5 nm, the MR ratio can be approximately 100%. However, when the MgO film thickness is decreased down to 0.9 nm, the MR ratio is decreased to not more than 10%.
In the conventional CPP-type MRAM, the element resistance of the magnetoresistive effect element itself is high because of the presence of the barrier layer, and to decrease the electric power consumption for the writing, the barrier layer must be thinned, sacrificing the output characteristics. On the other hand, in the CIP-type MRAM according to the present embodiment, the presence of the barrier layer is irrelevant to the electric power consumption for the writing, and taking into consideration only the applied voltage for the reading, the magnetoresistive effect element can be designed, forming the barrier layer of a film thickness for the high output. The S/N ratio can be much improved in comparison with that of the CPP-type MRAM.
Next, the write speed of the magnetoresistive effect element will be discussed.
In the CIP-type MRAM according to the present embodiment, when a sectional area of the free magnetization layer 52 is S=240 nm×10 nm, and a write current Iw is Iw=Jc×S=3.12 mA, the magnetic domain wall was shifted by about 1.5 μm when a 0.5 msec write current pulse was applied. The average speed of the magnetic domain wall evaluated based on this result is 3 m/sec.
When it is assumed that a length of the memory part of the free magnetization layer 52 of the magnetoresistive effect element is 200 nm, a time required to shift the magnetic domain wall by this distance is 67 nsec. Considering that the write speed of the flash memory is in the μsec order, the write speed of the CIP-type MRAM according to the present embodiment is practically sufficiently high.
Then, the method for fabricating the magnetic memory device according to the present embodiment will be explained with reference to
First, the device isolation film 12 for defining a device region is formed on a silicon substrate 10 by, e.g., STI (Shallow Trench Isolation) method.
Then, in the device region defined by the device isolation film 12, a select transistor including the gate electrode 14 and the source/drain regions 16, 18 is formed in the same way as the usual MOS transistor fabricating method (
Next, a silicon oxide film is deposited by, e.g., CVD method, on the silicon substrate 10 with the select transistor formed on, and the surface thereof is planarized by CMP method to form the inter-layer insulating film 20 of the silicon oxide film.
Next, by photolithography and dry etching, a contact hole is formed in the inter-layer insulating film 20 down to the source/drain region 16.
Next, a titanium nitride film as the barrier metal and a tungsten film are deposited by, e.g., CVD method, and these conductive films are etched back or polished back to form the contact plug 24 buried in the contact hole 22 and electrically connected to the source/drain region 16.
Next, a conductive film is deposited on the inter-layer insulating film 20 with the contact plug 24 buried in and patterned to form a source line 26 electrically connected to the source/drain region 16 via the contact plug 24 (
Then, a silicon oxide film is deposited by, e.g., CVD method, on the inter-layer insulating film 20 with the source line 26 formed on, and the surface thereof is planarized by CMP method to form the inter-layer insulating film 28 of the silicon oxide film.
Next, a conductive film is deposited on the inter-layer insulating film 28 and patterned to from the read bit line 30 (
Then, on the inter-layer insulating film 28 with the read bit line 30 formed on, a silicon oxide film is deposited by, e.g., CVD method, and the surface thereof is planarized by CMP method to form the inter-layer insulating film 32 of the silicon oxide film.
Then, a contact hole 34 is formed in the inter-layer insulating film 32 down to the read bit line 30.
Then, a titanium nitride film as the barrier metal and a tungsten film are deposited, and these conductive films are etched back or polished back to form the contact plug 36 buried in the contact hole 34 and electrically connected to the read bit line 30 (
Next, on the inter-layer insulating film 32 with the contact plug, 36 buried in, a Ta film, a PtMn film, a CoFe film, an Ru film, a CoFeB film and an MgO film are sequentially deposited on the inter-layer insulating film 32 with the contact plug 36 buried in.
Next, the MgO film, the CoFeB film, the Ru film, the CoFe film and the PtMn film are patterned to form the anti-ferromagnetic layer 40 of the PtMn film formed on the Ta film, the pinned magnetization layer 42 formed on the anti-ferromagnetic layer 40 and formed of the synthetic ferrimagnetic structure of the layer film of the CoFeB film 42c/the Ru film 42b/the CoFe film 42a, and the barrier layer 50 of the MgO film formed on the pinned magnetization layer 42.
Then, the Ta film is patterned by photolithography and dry etching to form the lower electrode layer 38 of the Ta film (
Next, on the inter-layer insulating film 32 with the lower electrode layer 38, the anti-ferromagnetic layer 40, the pinned magnetization layer 42 and the barrier layer 50 formed on, a silicon oxide film is deposited by, e.g., CVD method, and the surface thereof is polished by CMP method until the barrier layer 50 is exposed to form the inter-layer insulating film 44 of the silicon oxide film.
Next, by photolithography and dry etching, the contact hole 46 is formed in the inter-layer insulating film 44 down to the source/drain region 18.
Next, a titanium nitride film as the barrier metal and a tungsten film are deposited by, e.g., CVD method, and these conductive films are etched back or polished back to form the contact plug 48 buried in the contact hole 46 and electrically connected to the source/drain region 18 (
Next, on the inter-layer insulating film 44 with the contact plug 48 buried in, an NiFe film is deposited by, e.g., sputtering method.
Next, the NiFe film is patterned by photolithography and dry etching to form the free magnetization layer 52 of the NiFe film on the barrier layer 50.
Thus, the magnetoresistive effect element 54 of the TMR structure including the anti-ferromagnetic layer 40, the pinned magnetization layer 42, the barrier layer 50 and the free magnetization layer 52 is formed (
The anti-ferromagnetic layer 40 may be formed of, e.g., an anti-ferromagnetic material containing one of Re, Ru, Rh, Pd, IrPt, Cr, Fe, Ni, Cu, Ag and Au, and Mn, e.g., PtMn, PdPtMn, IrMn, RhMn, RuMn, FeMn or others.
The pinned magnetization layer 42 may be formed of a ferromagnetic material containing one of Co, Fe and Ni, e.g., CoFe, NiFe or others. With the synthetic ferrimagnetic structure formed, a non-magnetic material, such as Ru, Rh, Cr or others, may be used as the coupling film.
The barrier layer 50 may be formed of an oxide material, oxynitride material and nitride material containing one of Mg, Al, Hf, Ti, V, Ta, and Si, e.g., MgO, AlO, AlN, HfO, TiO, VO, TaO, SiO or others.
The free magnetization layer 52 may be formed of a ferromagnetic material containing one of Co, Fe and Ni, e.g., CoFeB, CoFeNi, CoFeSi, CoFeBSi, FeB, CoFe, NiFe or others.
On the inter-layer insulating film 44 with the magnetoresistive effect element 54 formed in, a silicon oxide film is deposited by, e.g., CVD method, and then the surface thereof is planarized by CMP method to form the inter-layer insulating film 56 of the silicon oxide film.
Then, by photolithography and dry etching, the contact hole 58 is formed in the inter-layer insulating film 56 down to the magnetoresistive effect element 54.
Then, a titanium nitride film as the barrier metal and a tungsten film are deposited by, e.g., CVD method, and these conductive films are etched back or polished back to form the contact plug 60 buried in the contact hole 58 and electrically connected to the read bit line 30.
Next, on the inter-layer insulating film 56 with the contact plug 60 buried in, a conductive film is deposited and patterned to form the write bit line 62 (
Then, insulating layers, interconnection layers, etc. are formed thereon as required, and the magnetic memory device is completed.
As described above, according to the present embodiment, in the magnetoresistive effect element comprising the pinned magnetization layer having the magnetization pinned in a first direction, the barrier layer formed on the pinned magnetization layer, and the free magnetization layer on the barrier layer and having a first magnetic domain magnetized in the first direction and a second magnetic domain magnetized in a second direction opposite to the first direction, memory information is written in the magnetoresistive effect element by flowing write current in the free magnetization layer in the in-plane direction to thereby shift the magnetic domain wall between the first magnetic domain and the second magnetic domain to thereby control a magnetization direction of a part of the free magnetization layer, opposed to the pinned magnetization layer, whereby it is not necessary that the write current is flowed via the barrier layer. This prevents the degradation of the barrier layer and allows the barrier layer to last long. Resultantly, the reliability of the magnetic memory device can be improved.
The write current is not flowed via the barrier layer, which allows the barrier layer to be thicker in comparison with that of the conventional spin injection magnetization reversal type magnetoresistive effect element, whereby the MR ratio of the magnetoresistive effect element is increased, and the S/N ratio of the output can be improved.
The present invention is not limited to the above-described embodiments and can cover other various modifications.
For example, in the above-described embodiments, the present invention is applied to the magnetic memory device including TMR-type magnetoresistive effect elements. However, the present invention is also applicable to magnetic memory devices including GMR-type magnetoresistive effect elements. In this case, in place of the barrier layer 50, a conductive non-magnetic layer may be provided. The pinned magnetization layer 42 and the free magnetization layer 52 may be oppositely positioned the former on the latter.
In the above-described embodiments, the pinned magnetization layer 42 has the synthetic ferrimagnetic structure of CoFeB/Ru/CoFe to thereby decrease the leakage magnetic field from the pinned magnetization layer 42. However, the pinned magnetization layer may have a singly-layer structure of, e.g., CoFe.
In the above-described embodiment, the present invention is applied to a magnetic memory device comprising a memory cell including one select transistor and one magnetoresistive effect element. However, the structure of the memory cell is not limited to the above. The present invention is characterized mainly by the structure of the magnetoresistive effect element, and as far as a magnetic memory device includes the magnetoresistive effect element according to the present invention, the structures of the memory cells, the arrangement of the signal lines and other structures are not limited to the above.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2006-093446 | Mar 2006 | JP | national |
