Patent Application
20160163369
This U.S. non-provisional patent application claims priority under 35 U.S.C. §119 to Korean Patent Application No. 10-2014-0175814, filed on Dec. 9, 2014, in the Korean Intellectual Property Office, the entire contents of which are hereby incorporated by reference.
Example embodiments of the inventive concepts relate to a magnetic memory device and a method of fabricating the same, and in particular, to a magnetic memory device, in which a magnetic tunnel junction with a free magnetic layer and a pinned magnetic layer is provided, and a method of fabricating the same.
Due to their small-size, multifunctionality, and/or low-cost characteristics, semiconductor devices are increasingly being used in consumer, commercial and other electronic devices. For example, semiconductor memory devices for storing data are widely used in various electronic devices. Recently, next-generation semiconductor memory devices (e.g., magnetic memory devices) are being developed for high-speed and non-volatile data-storing operations.
The magnetic memory device may include a magnetic tunnel junction MTJ. A magnetic tunnel junction may include two magnetic layers and a tunnel barrier layer interposed therebetween. Resistance of the magnetic tunnel junction may vary depending on magnetization orientations of the magnetic layers. For example, the resistance of the magnetic tunnel junction may be higher when the magnetic layers have anti-parallel magnetization orientations than when they have parallel magnetization orientations. Such a difference in resistance can be used for data storing operations of the magnetic memory device.
According to an example embodiment of the inventive concepts, a semiconductor device may include magnetic tunnel junctions provided spaced apart from each other on a substrate, each of the magnetic tunnel junctions including a free magnetic pattern, a first pinned magnetic pattern, and a tunnel barrier pattern therebetween, and a separation structure interposed between the magnetic tunnel junctions. The separation structure may include a second pinned magnetic pattern and a first insulating pattern stacked on the substrate.
In an example embodiment, the second pinned magnetic pattern may have a top surface positioned at a lower level than those of the magnetic tunnel junctions.
In an example embodiment, the second pinned magnetic pattern may have a bottom surface positioned at a higher level those of the magnetic tunnel junctions.
In an example embodiment, the semiconductor device may further include a capping layer provided to cover side surfaces of the magnetic tunnel junctions. The magnetic tunnel junctions and the second pinned magnetic pattern may be spaced apart from each other with the capping layer interposed therebetween.
In an example embodiment, the capping layer may extend to be interposed between the separation structure and the substrate, and the second pinned magnetic pattern may have a bottom surface in direct contact with the capping layer.
In an example embodiment, the separation structure may further include a second insulating pattern, which is vertically spaced apart from the first insulating pattern with the second pinned magnetic pattern interposed therebetween.
In an example embodiment, the semiconductor device may further include bottom electrodes provided below the magnetic tunnel junctions and top electrodes provided on the magnetic tunnel junctions. When viewed in plan view, each of the magnetic tunnel junctions may be overlapped with a corresponding one of the bottom electrodes and a corresponding one of the top electrodes.
In an example embodiment, the second pinned magnetic pattern may be stacked on the first insulating pattern and may have a top surface substantially coplanar with those of the top electrodes.
In an example embodiment, each of the magnetic tunnel junctions may further include a third pinned magnetic pattern, the first and third pinned magnetic patterns may be vertically spaced apart from each other with the free magnetic pattern interposed therebetween.
In an example embodiment, the first and second pinned magnetic patterns may have first and second magnetization directions, respectively, which is parallel, antiparallel, or perpendicular to each other, and each of which is fixed.
In an example embodiment, the second pinned magnetic pattern may include a plurality of patterns, which are provided spaced apart from each other, between the magnetic tunnel junctions. When viewed in plan view, the magnetic tunnel junctions and the patterns of the second pinned magnetic pattern may be alternatingly arranged in a specific direction.
In an example embodiment, when viewed in plan view, the separation structure extends in between the magnetic tunnel junctions to enclose each of the magnetic tunnel junctions.
In an example embodiment, the semiconductor device may further include a cell gate electrode provided on the substrate, a first impurity region and a second impurity region provided in portions of the substrate positioned at both sides of the cell gate electrode, a source line coupled to the first impurity region, and a contact coupled to the second impurity region. The contact may be connected to a corresponding one of the magnetic tunnel junctions.
In an example embodiment, when viewed in plan view, the separation structure may be overlapped with the source line.
According to another example embodiment of the inventive concepts, a semiconductor device may include magnetic tunnel junctions provided spaced apart from each other on a substrate, each of the magnetic tunnel junctions including a free magnetic pattern, a first pinned magnetic pattern, and a tunnel barrier pattern therebetween, and second pinned magnetic patterns spaced apart from each other and interposed between the magnetic tunnel junctions. When viewed in plan view, the magnetic tunnel junctions and the second pinned magnetic patterns may be alternatingly arranged in a specific direction.
In an example embodiment, the magnetic tunnel junctions may be arranged along first and second directions crossing each other to have a two-dimensional arrangement. The second pinned magnetic patterns may be arranged between the magnetic tunnel junctions and in a third direction crossing both of the first and second directions. Here, all of the first, second, and third directions may be parallel to a top surface of the substrate.
In an example embodiment, the semiconductor device may further include a capping layer covering side surfaces of the magnetic tunnel junctions and extending in between the second pinned magnetic patterns and the substrate, and top electrodes provided on the magnetic tunnel junctions. The second pinned magnetic patterns may have bottom surfaces, which are in direct contact with a top surface of the capping layer, and top surfaces, which are substantially coplanar with those of the top electrodes.
A semiconductor device may include magnetic tunnel junctions provided spaced apart from each other on a substrate, each of the magnetic tunnel junctions including a free magnetic pattern, a first pinned magnetic pattern, and a tunnel barrier pattern therebetween; bottom electrodes provided below the magnetic tunnel junctions and overlapped with the magnetic tunnel junctions, respectively, when viewed in plan view; and a second pinned magnetic pattern provided to fill gap regions between the bottom electrodes.
In an example embodiment, the second pinned magnetic pattern may have a top surface coplanar with those of the bottom electrodes. When viewed in plan view, the second pinned magnetic pattern may be provided to enclose the magnetic tunnel junctions.
In an example embodiment, the second pinned magnetic pattern may have side surfaces in direct contact with those of the bottom electrodes.
In an example embodiment, the semiconductor device may further include a capping layer covering side surfaces of the magnetic tunnel junctions and an interlayered insulating layer on the capping layer. When viewed in a vertical section, the capping layer may be interposed between the second pinned magnetic pattern and the interlayered insulating layer.
In an example embodiment, the semiconductor device may further include a cell gate electrode provided on the substrate, a first impurity region and a second impurity region provided in portions of the substrate positioned at both sides of the cell gate electrode, a source line coupled to the first impurity region, and a contact coupled to the second impurity region. The contact may be connected to a corresponding one of the magnetic tunnel junctions. When viewed in plan view, the second pinned magnetic pattern may be overlapped with the source line and is spaced apart from the contact.
Example embodiments of the inventive concepts will be more clearly understood from the following brief description taken in conjunction with the accompanying drawings. The accompanying drawings represent non-limiting, example embodiments as described herein.
It should be noted that these figures are intended to illustrate the general characteristics of methods, structure and/or materials utilized in certain example embodiments and to supplement the written description provided below. These drawings are not, however, to scale and may not precisely reflect the precise structural or performance characteristics of any given embodiment, and should not be interpreted as defining or limiting the range of values or properties encompassed by example embodiments. For example, the relative thicknesses and positioning of molecules, layers, regions and/or structural elements may be reduced or exaggerated for clarity. The use of similar or identical reference numbers in the various drawings is intended to indicate the presence of a similar or identical element or feature.
Example embodiments of the inventive concepts will now be described more fully with reference to the accompanying drawings, in which example embodiments are shown. Example embodiments of the inventive concepts may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those of ordinary skill in the art. In the drawings, the thicknesses of layers and regions are exaggerated for clarity. Like reference numerals in the drawings denote like elements, and thus their description will be omitted.
It will be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present. Like numbers indicate like elements throughout. As used herein the term “and/or” includes any and all combinations of one or more of the associated listed items. Other words used to describe the relationship between elements or layers should be interpreted in a like fashion (e.g., “between” versus “directly between,” “adjacent” versus “directly adjacent,” “on” versus “directly on”).
It will be understood that, although the terms “first”, “second”, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of example embodiments.
Spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as “below” or “beneath” other elements or features would then be oriented “above” the other elements or features. Thus, the exemplary term “below” can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of example embodiments. As used herein, the singular forms “a,” “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises”, “comprising”, “includes” and/or “including,” if used herein, specify the presence of stated features, integers, steps, operations, elements and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and/or groups thereof.
Example embodiments of the inventive concepts are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of example embodiments. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, example embodiments of the inventive concepts should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an implanted region illustrated as a rectangle may have rounded or curved features and/or a gradient of implant concentration at its edges rather than a binary change from implanted to non-implanted region. Likewise, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation takes place. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of example embodiments.
As appreciated by the present inventive entity, devices and methods of forming devices according to various embodiments described herein may be embodied in microelectronic devices such as integrated circuits, wherein a plurality of devices according to various embodiments described herein are integrated in the same microelectronic device. Accordingly, the cross-sectional view(s) illustrated herein may be replicated in two different directions, which need not be orthogonal, in the microelectronic device. Thus, a plan view of the microelectronic device that embodies devices according to various embodiments described herein may include a plurality of the devices in an array and/or in a two-dimensional pattern that is based on the functionality of the microelectronic device.
The devices according to various embodiments described herein may be interspersed among other devices depending on the functionality of the microelectronic device. Moreover, microelectronic devices according to various embodiments described herein may be replicated in a third direction that may be orthogonal to the two different directions, to provide three-dimensional integrated circuits.
Accordingly, the cross-sectional view(s) illustrated herein provide support for a plurality of devices according to various embodiments described herein that extend along two different directions in a plan view and/or in three different directions in a perspective view. For example, when a single active region is illustrated in a cross-sectional view of a device/structure, the device/structure may include a plurality of active regions and transistor structures (or memory cell structures, gate structures, etc., as appropriate to the case) thereon, as would be illustrated by a plan view of the device/structure.
Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which example embodiments of the inventive concepts belong. It will be further understood that terms, such as those defined in commonly-used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
Referring to
The selection device SW may be configured to selectively control a current flow of an electric current passing through the magnetic tunnel junction MTJ. For example, the selection device SW may be one of a diode, a PNP bipolar transistor, an NPN bipolar transistor, an NMOS field effect transistor (FET), and a PMOS FET. In the case that the selection device SW is a three-terminal switching device, such as bipolar transistors and MOSFETs, an additional interconnection line (not shown) may be connected to the selection device SW.
The magnetic tunnel junction MTJ may include a first magnetic structure MS1, a second magnetic structure MS2, and a tunnel barrier pattern TBR therebetween. Each of the first and second magnetic structures MS1 and MS2 may include at least one magnetic layer made of a magnetic material. In example embodiments, as shown in
Referring to
Electrical resistance of the magnetic tunnel junction MTJ may be sensitive to a relative orientation of magnetization directions of the free and pinned magnetic patterns FL and PL. For example, the electrical resistance of the magnetic tunnel junction MTJ may be much greater when the relative orientation is antiparallel than when parallel. This means that the electrical resistance of the magnetic tunnel junction MTJ can be controlled by changing the magnetization direction of the free magnetic pattern FL. The magnetic memory devices according to example embodiments of the inventive concept may be realized based on this data-storing mechanism.
As shown in
As an example, each of the first and second magnetic structures MS1 and MS2 may include at least one magnetic layer, whose magnetization direction is substantially perpendicular to a top surface of the substrate 100. In this case, the magnetic tunnel junction MTJ may be a first type of magnetic tunnel junction MTJ1, in which the pinned and free magnetic patterns PL and FL are provided in the first and second magnetic structures MS1 and MS2, respectively, as shown in
In addition, each of the first and second magnetic structures MS1 and MS2 may include at least one magnetic layer, whose magnetization direction is substantially parallel to the top surface of the substrate 100. In this case, the magnetic tunnel junction MTJ may be a third type of magnetic tunnel junction MTJ3, in which the pinned and free magnetic patterns PL and FL are provided in the first and second magnetic structures MS1 and MS2, respectively, as shown in
Referring to
Isolation gate electrodes IG may be disposed spaced apart from each other with a pair of cell gate electrodes CG interposed therebetween. The isolation gate electrodes IG may be spaced apart from each other in the first direction D1 and may extend in the second direction D2. Isolation gate dielectric layers 101i may be respectively disposed between the isolation gate electrodes IG and the substrate 100.
Gate hard mask patterns 104 may be disposed on the cell and isolation gate electrodes CG and IG, respectively. Each of the gate hard mask patterns 104 may have a top surface substantially coplanar with that of the substrate 100.
When the semiconductor memory device is operated, an isolation voltage may be applied to at least one of the isolation gate electrodes IG. This makes it possible to prevent an unintended channel region from being formed below the isolation gate electrodes IG. In other words, the isolation voltage may allow an isolation channel region positioned below each of the isolation gate electrodes IG to be in a turn-off state, and thus, an active region may be defined between the isolation gate electrodes IG.
The cell gate electrodes CG may include at least one of, for example, doped semiconductor materials (e.g., doped silicon), metals (e.g., tungsten, aluminum, titanium, and/or tantalum), conductive metal nitrides (e.g., titanium nitride, tantalum nitride, and/or tungsten nitride), or metal-semiconductor compounds (e.g., metal silicide). The isolation gate electrodes IG may include the same material as the cell gate electrodes CG. The cell gate dielectric layers 101c and the isolation gate dielectric layers 101i may include, for example, at least one of oxide (e.g., silicon oxide), nitride (e.g., silicon nitride), oxynitride (e.g., silicon oxynitride), and/or a high-k dielectric (e.g., insulating metal oxides such as hafnium oxide or aluminum oxide). The gate hard mask patterns 104 may include at least one of oxide (e.g., silicon oxide), nitride (e.g., silicon nitride), or oxynitride (e.g., silicon oxynitride).
First and second impurity regions 102a and 102b may be provided at both sides of each of the cell gate electrodes CG. The first and second impurity regions 102a and 102b may serve as source and drain regions of each of the transistors. The pair of cell gate electrodes CG may share the first impurity region 102a provided between the pair of cell gate electrodes CG. The first and second impurity regions 102a and 102b may be doped to have a different conductivity type from that of the substrate 100.
A source line SL may be provided on the substrate 100 between each pair of cell gate electrodes CG. The source line SL may be electrically coupled to the first impurity region 102a. A pair of selection devices disposed adjacent to each other may share one of the source lines SL interposed therebetween. The source line SL may include at least one of, for example, doped semiconductor materials (e.g., doped silicon), metals (e.g., tungsten, aluminum, titanium, and/or tantalum), conductive metal nitrides (e.g., titanium nitride, tantalum nitride, and/or tungsten nitride), or metal-semiconductor compounds (e.g., metal silicide).
A first interlayered insulating layer 106 may be provided on the substrate 100 to cover the cell and isolation gate electrodes CG and IG and the source line SL. The first interlayered insulating layer 106 may be formed of or include, for example, a silicon oxide layer. Contacts 110 may be provided through the first interlayered insulating layer 106 and may be coupled to the second impurity regions 102b, respectively. In other words, the first impurity region 102a may be coupled to the source line SL, and the second impurity regions 102b may be coupled to the contacts 110. Each of the contacts 110 may have a top surface substantially coplanar with that of the first interlayered insulating layer 106. The contacts 110 may include at least one of metals, conductive metal nitrides, or doped semiconductor materials.
A buried insulating layer 114 may be provided on the first interlayered insulating layer 106. The buried insulating layer 114 may be formed of or include, for example, silicon nitride. Conductive pads 112 may be provided through the buried insulating layer 114 and may be connected to the contacts 110, respectively. Each of the conductive pads 112 may have a top surface substantially coplanar with that of the buried insulating layer 114. The conductive pads 112 may include at least one of metals, conductive metal nitrides, or doped semiconductor materials. The contacts 110 and the conductive pads 112 may be used to connect the second impurity regions 102b to a magnetic tunnel junction, which will be formed in a subsequent process.
Bottom electrodes BE may be provided on the buried insulating layer 114 and may be coupled to the conductive pads 112, respectively. Magnetic tunnel junctions MTJ may be disposed on and connected to the bottom electrodes BE, respectively. Top electrodes TE may be provided on and coupled to the magnetic tunnel junctions MTJ, respectively. The bottom electrodes BE and the top electrodes TE may include at least one of metals, conductive metal nitrides, or doped semiconductor materials.
The magnetic tunnel junctions MTJ may be electrically connected to the second impurity regions 102b through the bottom electrodes BE, the conductive pads 112, and the contacts 110. As shown in
The magnetic tunnel junctions MTJ may include first magnetic structures MS1, which are respectively coupled to the bottom electrodes BE and second magnetic structures MS2, which are respectively coupled to the top electrodes TE. In example embodiments, the first magnetic structures MS1 may include first pinned magnetic patterns PL1, and the second magnetic structures MS2 may include first free magnetic patterns FL1, as will be described in more detail with reference to
The magnetic tunnel junctions MTJ may further include a tunnel bather patterns TBR disposed between the first magnetic structures MS1 and the second magnetic structures MS2. The magnetic tunnel junctions MTJ will be described in more detail with reference to
A capping layer 120 may be provided to cover the side surfaces of the magnetic tunnel junctions MTJ. The capping layer 120 may be extended from the sidewalls of the magnetic tunnel junctions MTJ to cover sidewalls of the top electrodes TE, sidewalls of the bottom electrodes BE, and a top surface of the buried insulating layer 114. The capping layer 120 may have a top surface substantially coplanar with those of the top electrodes TE. The capping layer 120 may include at least one of tantalum oxide, magnesium oxide, titanium oxide, zirconium oxide, hafnium oxide, or zinc oxide.
Separation structures SS may be interposed between the magnetic tunnel junctions MTJ. Each of the separation structures SS may include a second pinned magnetic pattern PL2 and a first insulating pattern 135, which are sequentially stacked on the capping layer 120. The first insulating patterns 135 may be formed of or include, for example, a silicon oxide layer. The separation structures SS may be spaced apart from the magnetic tunnel junctions MTJ with the capping layer 120 interposed therebetween. The separation structures SS may have top surfaces coplanar with those of the top electrodes TE.
As shown in
As shown in
A second interlayered insulating layer 130 may be formed on the buried insulating layer 114 to fill gap regions between or around the lower and top electrodes BE and TE, the magnetic tunnel junctions MTJ, the capping layer 120, and the separation structures SS. As shown in
In example embodiments, the first insulating patterns 135, which are provided to define the second pinned magnetic patterns PL2, may be continuously connected to the second interlayered insulating layer 130, and in this case, the first insulating patterns 135 and second interlayered insulating layer 130 may constitute a single body.
A third interlayered insulating layer 140 and bit lines BL may be provided on the second interlayered insulating layer 130 and the separation structures SS. The bit lines BL may be provided in the third interlayered insulating layer 140. The bit lines BL may be spaced apart from each other in the second direction D2 and may extend parallel to the first direction D1. Each of the bit lines BL may be coupled to a plurality of top electrodes TE arranged parallel to the first direction D1. The bit lines BL may be formed of or include, for example, at least one of metals or conductive metal nitrides.
Referring to
For example, the first magnetic structure MS1 may include the first pinned magnetic pattern PL1. In other words, the first pinned magnetic pattern PL1 may be provided between the bottom electrode BE (e.g., of
The second magnetic structure MS2 may include the first free magnetic pattern FL1 provided on the tunnel barrier pattern TBR. For example, the first free magnetic pattern FL1 may be provided between the tunnel barrier pattern TBR and the top electrode TE (e.g., of
The second pinned magnetic pattern PL2 may be provided adjacent to the magnetic tunnel junction MTJ. The magnetic tunnel junction MTJ and the second pinned magnetic pattern PL2 may be disposed to have substantially the same disposition and arrangement as that described with reference to
The first and second pinned magnetic patterns PL1 and PL2 may have a magnetization direction substantially perpendicular to the top surface of the substrate 100. Similarly, a magnetization direction of the first free magnetic pattern FL1 may be substantially perpendicular to the top surface of the substrate 100.
In some aspect of the inventive concept, the first pinned magnetic pattern PL1 may be configured to have an easy axis that is substantially perpendicular to the top surface of the substrate 100. The first pinned magnetic pattern PL1 may have a first magnetization direction MD1 that is fixed. The second pinned magnetic pattern PL2 may also be configured to have an easy axis that is substantially perpendicular to the top surface of the substrate 100. The second pinned magnetic pattern PL2 may have a second magnetization direction MD2 that is fixed. The first and second magnetization directions MD1 and MD2 may not be the same. For example, the second magnetization direction MD2 may be antiparallel to the first magnetization direction MD1. In this case, magnetic fields generated from the first and second pinned magnetic patterns PL1 and PL2 may be cancelled to each other and a net or resultant magnetic field from the first and second pinned magnetic patterns PL1 and PL2 may have a lowered magnitude. This makes it possible to reduce influence of the first and second pinned magnetic patterns PL1 and PL2 on a magnetization property of the first free magnetic pattern FL1.
The first free magnetic pattern FL1 may have a magnetization direction which is parallel or antiparallel to the first magnetization direction MD1, and the switching of the magnetization direction of the first free magnetic pattern FL1 may be achieved through a programming operation. For example, the switching of the magnetization direction of the first free magnetic pattern FL1 may be controlled by a spin torque transfer (STT) programming operation. In other words, the magnetization direction of the first free magnetic pattern FL1 may be switched using electrons constituting a program current, based on a spin torque transfer phenomenon.
In example embodiments, the second pinned magnetic pattern PL2 may be provided between the magnetic tunnel junctions MTJ. For example, the second pinned magnetic pattern PL2 may be provided at a position horizontally spaced apart from the first pinned magnetic pattern PL1 and the first free magnetic pattern FL1, independent of the magnetic tunnel junction MTJ, and thus, it is possible to reduce a total thickness of the magnetic tunnel junction MTJ. Further, this makes it possible to easily perform a patterning process for forming the magnetic tunnel junction MTJ. In addition, once the magnetization direction of the first free magnetic pattern FL1 is switched, the switched magnetization direction of the first free magnetic pattern FL1 may be constrained (e.g., to be parallel to the second magnetization direction MD2) by the second pinned magnetic pattern PL2, and this makes it possible to improve stability of the magnetic tunnel junction MTJ.
Referring to
Referring to
Referring to
The non-magnetic metal pattern 165 may include a non-magnetic metal material. For example, the non-magnetic metal material may be one of Hf, Zr, Ti, Ta, and any alloy thereof. The non-magnetic metal pattern 165 may be configured to allow the third pinned magnetic pattern PL3 to be magnetically coupled with the first free magnetic pattern FL1. However, in other example embodiments, the non-magnetic metal pattern 165 may be omitted.
Referring to
The non-magnetic metal pattern 165 may include a non-magnetic metal material. Due to the presence of the non-magnetic metal pattern 165, the second free magnetic pattern FL2 may be magnetically coupled with the first free magnetic pattern FL1 in such a way that the second free magnetic pattern FL2 has a magnetization direction parallel to that of the first free magnetic pattern FL1.
The second free magnetic pattern FL2 may include a perpendicular magnetic material (for example, at least one of the above materials enumerated for the first free magnetic pattern FL1 in
Referring to
The pinning pattern 190 may include an antiferromagnetic material. For example, the pinning pattern 190 may include at least one of platinum manganese (PtMn), iridium manganese (IrMn), manganese oxide (MnO), manganese sulfide (MnS), manganese tellurium (MnTe), or manganese fluoride (MnF).
The first pinned magnetic pattern PL1 may include a ferromagnetic material. For example, the first pinned magnetic pattern PL1 may include at least one cobalt-iron-boron (CoFeB), cobalt-iron (CoFe), nickel-iron (NiFe), cobalt-iron-platinum (CoFePt), cobalt-iron-palladium (CoFePd), cobalt-iron-chromium (CoFeCr), cobalt-iron-terbium (CoFeTb), or cobalt-iron-nickel (CoFeNi).
The second magnetic structure MS2 may include the first free magnetic pattern FL1 provided on the tunnel barrier pattern TBR. In the present embodiment, the second magnetic structure MS2 may be configured to include a free magnetic pattern FL constituting the third type of magnetic tunnel junction MTJ3 shown in
The first free magnetic pattern FL1 may be formed of a ferromagnetic material containing at least one of cobalt (Co), iron (Fe), or nickel (Ni). For example, the first free magnetic pattern FL1 may include at least one of CoFeB, CoFe, or CoFeNi.
The second pinned magnetic pattern PL2 may be provided adjacent to the magnetic tunnel junction MTJ. The second pinned magnetic pattern PL2 may include an in-plane magnetic material (for example, at least one of the above materials enumerated for the first pinned magnetic pattern PL1).
The second pinned magnetic pattern PL2 may have a second magnetization direction MD2 that is fixed. As an example, the first magnetization direction MD1 may be antiparallel to the second magnetization direction MD2. However, example embodiments of the inventive concepts may not be limited thereto, and for example, the first magnetization direction MD 1 may be parallel to the second magnetization direction MD2, as described with reference to
Referring to
Referring to
The isolation gate electrodes IG may be formed spaced apart from each other with the pair of cell gate electrodes CG interposed therebetween. The isolation gate electrodes IG may be spaced apart from each other in the first direction D1 and may extend in the second direction D2. The isolation gate dielectric layers 101i may be respectively formed between the isolation gate electrodes IG and the substrate 100.
The formation of the cell and isolation gate electrodes CG and IG may include forming gate recess regions. The gate recess regions may be formed in the substrate 100 to be spaced apart from each other in the first direction D1 and extend in the second direction D2. Thereafter, the cell and isolation gate dielectric layers 101c and 101i and the cell and isolation gate electrodes CG and IG may be formed to fill the gate recess regions.
The gate hard mask patterns 104 may be respectively formed on the cell and isolation gate electrodes CG and IG. The gate hard mask patterns 104 may be formed to fill the remaining empty spaces of the gate recess regions. A planarization process may be performed on the gate hard mask patterns 104, and as a result of the planarization process, the gate hard mask patterns 104 may be formed to have top surfaces substantially coplanar with that of the substrate 100.
The cell gate electrodes CG may include at least one of, for example, doped semiconductor materials (e.g., doped silicon), metals (e.g., tungsten, aluminum, titanium, and/or tantalum), conductive metal nitrides (e.g., titanium nitride, tantalum nitride, and/or tungsten nitride), or metal-semiconductor compounds (e.g., metal silicide). The isolation gate electrodes IG may include the same material as the cell gate electrodes CG. The cell gate dielectric layers 101c and the isolation gate dielectric layers 101i may include, for example, at least one of oxide (e.g., silicon oxide), nitride (e.g., silicon nitride), oxynitride (e.g., silicon oxynitride), and/or a high-k dielectric (e.g., insulating metal oxides such as hafnium oxide or aluminum oxide). The gate hard mask patterns 104 may include at least one of oxide (e.g., silicon oxide), nitride (e.g., silicon nitride), or oxynitride (e.g., silicon oxynitride).
The first and second impurity regions 102a and 102b may be formed at both sides of each of the cell gate electrodes CG. The first and second impurity regions 102a and 102b may be doped to have a different conductivity type from that of the substrate 100.
The source line SL may be formed on the substrate 100 between the pair of cell gate electrodes CG. The source line SL may be formed to be electrically connected to the first impurity region 102a between the pair of cell gate electrodes CG. The source line SL may include at least one of, for example, doped semiconductor materials (e.g., doped silicon), metals (e.g., tungsten, aluminum, titanium, and/or tantalum), conductive metal nitrides (e.g., titanium nitride, tantalum nitride, and/or tungsten nitride), or metal-semiconductor compounds (e.g., metal silicide).
The first interlayered insulating layer 106 may be formed on the substrate 100 to cover the cell and isolation gate electrodes CG and IG and the source line SL. The contacts 110 may be connected to the second impurity regions 102b through the first interlayered insulating layer 106. As an example, the first interlayered insulating layer 106 may be a silicon oxide layer, which may be formed by a chemical vapor deposition. The contacts 110 may be formed in such a way that each of them is connected to a corresponding one of the second impurity regions 102b, which are disconnected from the source line SL. The contacts 110 may include at least one of metals, conductive metal nitrides, or doped semiconductor materials.
The buried insulating layer 114 may be formed on the first interlayered insulating layer 106, and the conductive pads 112 may be formed through the buried insulating layer 114 and may be connected to the contacts 110, respectively. As an example, the buried insulating layer 114 may include a silicon nitride layer, which may be formed by a chemical vapor deposition. The conductive pads 112 may include at least one of metals, conductive metal nitrides, or doped semiconductor materials. A planarization process may be performed on the conductive pads 112, and as a result of the planarization process, the conductive pads 112 may be formed to have top surfaces substantially coplanar with that of the buried insulating layer 114.
A bottom electrode layer BEa and a magnetic tunnel junction layer MTJa may be sequentially formed on the conductive pads 112 and the buried insulating layer 114. The bottom electrode layer BEa may include at least one of metals, conductive metal nitrides, or doped semiconductor materials. The magnetic tunnel junction layer MTJa may include a first magnetic layer MS1a, a tunnel barrier layer TBRa, and a second magnetic layer MS2a sequentially deposited on the bottom electrode layer BEa. A metal mask layer may be formed on the magnetic tunnel junction layer MTJa and may be patterned to form the top electrodes TE. The metal mask layer may include at least one of metals, conductive metal nitrides, or doped semiconductor materials. An ion beam etching process or a dry etching process may be performed to form the top electrodes TE. The top electrodes TE may be formed to be overlapped with the conductive pads 112, respectively, when viewed in plan view.
Referring to
The magnetic tunnel junctions MTJ may include the first magnetic structures MS1 respectively connected to the bottom electrodes BE, the second magnetic structures MS2 respectively connected to the top electrodes TE, and the tunnel barrier patterns TBR disposed between the first and second magnetic structures MS1 and MS2. The magnetic tunnel junctions MTJ may be formed to be spaced apart from each other in the first and second directions D1 and D2, when viewed in plan view. The magnetic tunnel junctions MTJ may be formed to be overlapped with the conductive pads 112, respectively.
After the formation of the magnetic tunnel junctions MTJ, the capping layer 120 may be formed on the magnetic tunnel junctions MTJ. The capping layer 120 may be formed to cover sidewalls of the magnetic tunnel junctions MTJ and the bottom electrodes BE and a top surface of the buried insulating layer 114. The capping layer 120 may be formed of or include a metal oxide layer, which may be formed by a chemical vapor deposition process.
Referring to
Referring back to
A magnetic material may be deposited in the holes 136 to form the second pinned magnetic patterns PL2. The second pinned magnetic patterns PL2 may be formed to fill lower portions of the holes 136. When viewed in plan view, the second pinned magnetic patterns PL2 may be arranged two-dimensionally (i.e., spaced apart from each other in the first and second directions D1 and D2). In addition, the magnetic tunnel junctions MTJ and the second pinned magnetic patterns PL2 may be alternatingly arranged in the third direction D3. The third direction D3 may be a direction crossing both of the first and second directions D1 and D2 and being parallel to the top surface of the substrate 100.
An insulating layer (not shown) may be formed to fill upper portions of the holes 136. The insulating layer may be formed of or include, for example, a silicon oxide layer. The insulating layer may be formed to fill the holes 136 and cover the second interlayered insulating layer 130.
Thereafter, the insulating layer and the second interlayered insulating layer 130 may be planarized to form the first insulating patterns 135 exposing the top electrodes TE. The planarization process may be performed to remove the capping layer 120 remaining on the top surfaces of the top electrodes TE. As a result of the planarization process, the top electrodes TE may have top surfaces substantially coplanar with those of the second interlayered insulating layer 130 and the first insulating patterns 135.
The third interlayered insulating layer 140 may be formed on the second interlayered insulating layer 130. Thereafter, the bit lines BL may be formed in the third interlayered insulating layer 140. When viewed in plan view, the bit lines BL may be spaced apart from each other in the second direction D2 and extend in the first direction D1. Each of the bit lines BL may be coupled to a plurality of the top electrodes TE arranged parallel to the first direction D1. The bit lines BL may be formed of or include, for example, at least one of metals or conductive metal nitrides.
Referring to
The second pinned magnetic patterns PL2 may be provided to fill the recess regions. For example, the recess regions may be completely filled with the capping layer 120 and the second pinned magnetic pattern PL2. The second pinned magnetic patterns PL2 may be formed to have bottom surfaces in direct contact with the capping layer 120. The second pinned magnetic patterns PL2 may have top surfaces substantially coplanar with that of the buried insulating layer 114.
In the present embodiment, the first insulating patterns 135 and the second interlayered insulating layer 130 may be formed by the same process and may be continuously connected to each other to constitute a single insulating layer. Except for the difference described above, the magnetic memory device according to the present embodiment may be the same as that described with reference to
Referring to
Referring to
After the formation of the magnetic tunnel junctions MTJ, the capping layer 120 may be formed on the magnetic tunnel junctions MTJ. The capping layer 120 may be formed to cover side and bottom surfaces of the recess regions. The level of the top surface of the capping layer 120 may be lower in the recess regions than between a pair of the magnetic tunnel junctions MTJ separated from each other in the first direction D1.
Referring back to
The etch-back process may be performed in such a way that each of the second pinned magnetic patterns PL2 is formed, in a self-aligned manner, between the pair of magnetic tunnel junctions MTJ separated from each other in the third direction D3. In other words, when viewed in plan view, the magnetic tunnel junctions MTJ and the second pinned magnetic patterns PL2 may be alternatingly arranged along the third direction D3.
Next, the second interlayered insulating layer 130, the third interlayered insulating layer 140, and the bit lines BL may be formed. According to the present embodiment, the second interlayered insulating layer 130 may include portions, which are positioned on the second pinned magnetic patterns PL2 and are used as the first insulating patterns 135. Except for the difference described above, the magnetic memory device according to the present embodiment may be the same as that described with reference to
Referring to
As an example, top surfaces of the second pinned magnetic patterns PL2 may be positioned at a lower level than those of the magnetic tunnel junctions MTJ, and bottom surfaces of the second pinned magnetic patterns PL2 may be positioned at a higher level than those of the magnetic tunnel junctions MTJ. Except for the difference described above, the magnetic memory device according to the present embodiment may be the same as that described with reference to
The following is a description of a method for fabricating a magnetic memory device, according to the present embodiment. Description of an element or step previously described with reference to
Referring back to
For example, an insulating layer may be deposited to form the first insulating patterns 135 in lower portions of the holes 136. Thereafter, a magnetic material may be deposited on the first insulating patterns 135 to form the second pinned magnetic pattern PL2. Another insulating layer may be deposited on the second pinned magnetic patterns PL2 to form the second insulating pattern 137. The formation of the separation structures SS may further include a planarization process, which is performed on another insulating layer to expose the top electrodes TE.
Referring to
As an example, the second pinned magnetic patterns PL2 may have bottom surfaces positioned at a higher level than those of the magnetic tunnel junctions MTJ. The second pinned magnetic patterns PL2 may have top surfaces substantially coplanar with those of the top electrodes TE. Except for the difference described above, the magnetic memory device according to the present embodiment may be the same as that described with reference to
The following is a description of a method for fabricating a magnetic memory device, according to the present embodiment. Description of an element or step previously described with reference to
Referring back to
For example, an insulating layer may be deposited to form the first insulating patterns 135 in lower portions of the holes 136. Thereafter, a magnetic material may be deposited on the first insulating patterns 135 to form the second pinned magnetic pattern PL2. Here, the formation of the separation structures SS may further include a planarization process, which is performed on the magnetic material to expose the top electrodes TE.
Referring to
As an example, bottom surfaces of the second pinned magnetic patterns PL2 may be positioned at a lower level than those of the magnetic tunnel junctions MTJ, and top surfaces of the second pinned magnetic patterns PL2 may be positioned at a higher level than those of the magnetic tunnel junctions MTJ. Further, the top surfaces of the second pinned magnetic patterns PL2 may be substantially coplanar with those of the top electrodes TE. Except for the difference described above, the magnetic memory device according to the present embodiment may be the same as that described with reference to
The following is a description of a method for fabricating a magnetic memory device, according to the present embodiment. Description of an element or step previously described with reference to
Referring back to
The formation of the second pinned magnetic patterns PL2 may include depositing a magnetic material to fill the whole region of the holes 136 and then planarizing the magnetic material to expose the top electrodes TE.
Referring to
Unlike that described with reference to
The following is a description of a method for fabricating a magnetic memory device, according to the present embodiment. Description of an element or step previously described with reference to
Referring back to
Next, an insulating layer may be formed to cover the second pinned magnetic pattern PL2, the magnetic tunnel junctions MTJ, and the capping layer 120. Thereafter, the insulating layer may be planarized to form the first insulating pattern 135 exposing the top electrodes TE. When viewed in plan view, the first insulating pattern 135 may be provided to enclose each of the magnetic tunnel junctions MTJ, like the second pinned magnetic pattern PL2. The second pinned magnetic pattern PL2 and the first insulating pattern 135 may constitute the separation structure SS.
The third interlayered insulating layer 140 may be formed on the first insulating pattern 135. The bit lines BL may be formed in the third interlayered insulating layer 140. Except for the difference described above, the magnetic memory device according to the present embodiment may be the same as that described with reference to
Referring to
Unlike that described with reference to
The capping layer 120 may be provided to cover the side surfaces of the magnetic tunnel junctions MTJ. Further, the capping layer 120 may be extended to cover the top surface of the second pinned magnetic pattern PL2.
The second interlayered insulating layer 130 may be provided on the capping layer 120 to fill the gap regions between the magnetic tunnel junctions MTJ. The second interlayered insulating layer 130 may have a top surface substantially coplanar with those of the top electrodes TE. Except for this difference, the magnetic memory device according to the present embodiment may be the same as that described with reference to
Referring to
A magnetic material may be deposited to fill a gap between the bottom electrodes BE. Thereafter, the magnetic material may be planarized to form the second pinned magnetic pattern PL2 exposing the bottom electrodes BE. Regions between the bottom electrodes BE may be filled with the second pinned magnetic pattern PL2, which is provided in the form of a single body. When viewed in plan view, the second pinned magnetic pattern PL2 may be provided to enclose each of the bottom electrodes BE. For example, the second pinned magnetic pattern PL2 may be shaped like a grating or mesh.
Referring to
Referring to
Referring back to
[Application]
Referring to
Hereinafter, a memory system including a magnetic memory device according to example embodiments of inventive concepts will be described with reference to
The magnetic memory devices disclosed above may be encapsulated using various and diverse packaging techniques. For example, magnetic memory devices according to the aforementioned embodiments may be encapsulated using any one of a package on package (POP) technique, a ball grid array (BGA) technique, a chip scale package (CSP) technique, a plastic leaded chip carrier (PLCC) technique, a plastic dual in-line package (PDIP) technique, a die in waffle pack technique, a die in wafer form technique, a chip on board (COB) technique, a ceramic dual in-line package (CERDIP) technique, a plastic quad flat package (PQFP) technique, a small outline package (SOIC) technique, a shrink small outline package (SSOP) technique, a thin small outline package (TSOP) technique, a thin quad flat package (TQFP) technique, a system in package (SIP) technique, a multi-chip package (MCP) technique, a wafer-level fabricated package (WFP) technique and a wafer-level processed stack package (WSP) technique.
The package in which the magnetic memory device according to one of the above embodiments is mounted may further include at least one semiconductor device (e.g., a controller and/or a logic device) that controls the magnetic memory device.
According to exemplary embodiments of the inventive concepts, a magnetic memory device may include a magnetic tunnel junction and a pinned magnetic pattern horizontally separated from the magnetic tunnel junction. The pinned magnetic pattern allows the magnetic tunnel junction to be operated with higher stability, a lower operation current, and a higher operation speed. Further, since the pinned magnetic pattern is formed spaced apart from the magnetic tunnel junction in a horizontal direction, it is possible to reduce a total thickness of the magnetic tunnel junction and consequently improve structural stability of the magnetic tunnel junction.
While example embodiments of the inventive concepts have been particularly shown and described, it will be understood by one of ordinary skill in the art that variations in form and detail may be made therein without departing from the spirit and scope of the attached claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 10-2014-0175814 | Dec 2014 | KR | national |
