Patent Application
20190392879
The present invention relates to magnetic random access memory (MRAM) and more particularly to a magnetic memory element having a MgO isolation layer located at the side of the memory element to improve robustness to high temperature processing.
Magnetic Random Access Memory (MRAM) is a non-volatile data memory technology that stores data using magnetoresistive cells such as Magnetoresistive Tunnel Junction (MTJ) cells. At their most basic level, such MTJ elements include first and second magnetic layers that are separated by a thin, non-magnetic layer such as a tunnel barrier layer, which can be constructed of a material such as Mg—O. The first magnetic layer, which can be referred to as a reference layer, has a magnetization that is fixed in a direction that is perpendicular to that plane of the layer. The second magnetic layer, which can be referred to as a magnetic free layer, has a magnetization that is free to move so that it can be oriented in either of two directions that are both generally perpendicular to the plane of the magnetic free layer. Therefore, the magnetization of the free layer can be either parallel with the magnetization of the reference layer or anti-parallel with the direction of the reference layer (i.e. opposite to the direction of the reference layer).
The electrical resistance through the MTJ element in a direction perpendicular to the planes of the layers changes with the relative orientations of the magnetizations of the magnetic reference layer and magnetic free layer. When the magnetization of the magnetic free layer is oriented in the same direction as the magnetization of the magnetic reference layer, the electrical resistance through the MTJ element is at its lowest electrical resistance state. Conversely, when the magnetization of the magnetic free layer is in a direction that is opposite to that of the magnetic reference layer, the electrical resistance across the MTJ element is at its highest electrical resistance state.
The switching of the MTJ element between high and low resistance states results from electron spin transfer. An electron has a spin orientation. Generally, electrons flowing through a conductive material have random spin orientations with no net spin orientation. However, when electrons flow through a magnetized layer, the spin orientations of the electrons become aligned so that there is a net aligned orientation of electrons flowing through the magnetic layer, and the orientation of this alignment is dependent on the orientation of the magnetization of the magnetic layer through which they travel. When the orientations of the magnetizations of the free and reference layer are oriented in the same direction, the majority spin of the electrons in the free layer are is in the same direction as the orientation of the majority spin of the electrons in the reference layer. Because these electron spins are in generally the same direction, the electrons can pass relatively easily through the tunnel barrier layer. However, if the orientations of the magnetizations of the free and reference layers are opposite to one another, the spin of majority electrons in the free layer will be generally opposite to the majority spin of electrons in the reference layer. In this case, electrons cannot easily pass through the barrier layer, resulting in a higher electrical resistance through the MTJ stack.
Because the MTJ element can be switched between low and high electrical resistance states, it can be used as a memory element to store a bit of data. For example, the low resistance state can be read as an on or “1”, whereas the high resistance state can be read as a “0”. In addition, because the magnetic orientation of the magnetic free layer remains in its switched orientation without any electrical power to the element, it provides a robust, non-volatile data memory bit.
To write a bit of data to the MTJ cell, the magnetic orientation of the magnetic free layer can be switched from a first direction to a second direction that is 180 degrees from the first direction. This can be accomplished, for example, by applying a current through the MTJ element in a direction that is perpendicular to the planes of the layers of the MTJ element. An electrical current applied in one direction will switch the magnetization of the free layer to a first orientation, whereas switching the direction of the current and such that it is applied in a second direction will switch the magnetization of the free layer to a second, opposite orientation. Once the magnetization of the free layer has been switched by the current, the state of the MTJ element can be read by reading a voltage across the MTJ element, thereby determining whether the MTJ element is in a “1” or “0” bit state. Advantageously, once the switching electrical current has been removed, the magnetic state of the free layer will remain in the switched orientation until such time as another electrical current is applied to again switch the MTJ element. Therefore, the recorded date bit is non-volatile in that it remains intact in the absence of any electrical power.
The present invention provides a magnetic memory device that includes a magnetic memory element having a side and having a barrier layer. The magnetic memory device further includes a first isolation layer formed of a material that is substantially the same as the material of the barrier layer, and a second isolation layer arranged such that the first isolation layer separates the second isolation layer from the magnetic memory element.
The barrier layer and the first isolation layer can be constructed of magnesium oxide, whereas the second isolation layer can be formed of a material such as silicon oxide, which provides good dielectric properties, good hardness and resistance to corrosion and also has good properties for chemical mechanical polishing. A third isolation layer, which can be constructed of a material such as silicon nitride can be provided over the second insulation layer and can serve as a chemical mechanical polishing (CMP) stop layer to facilitate manufacture of the device.
In a magnetic memory device, magnetic memory elements are connected with circuitry such as CMOS circuitry that requires high temperature treatment to be performed after formation of the magnetic memory element. This high temperature treatment can include treatment at temperatures of around 400 degrees C. for extended periods of time. This high temperature treatment can cause Si diffusion into the barrier layer which greatly degrades spin tunneling properties and decreases performance. In addition, the high temperature treatment can cause the formation of crystals at the outer edges of the barrier layer which can lead to current shunting and reduced electrical resistance of the memory element.
The presence of the first isolation layer advantageously prevents Si from migrating from the other isolation layer or layer and diffusing into the barrier layer. The first isolation layer also advantageously prevents the problematic formation of crystals at the outer edges of the barrier layer which would act as current shunts and greatly degrade performance of the device.
As discussed, the first isolation layer can be constructed of substantially the same material as the barrier layer. For example, if the barrier layer is constructed of magnesium oxide, the first isolation layer can be constructed of magnesium oxide having an oxygen content that is within plus or minus five atomic percent of that of the barrier layer.
These and other features and advantages of the invention will be apparent upon reading of the following detailed description of the embodiments taken in conjunction with the figures in which like reference numeral indicate like elements throughout.
For a fuller understanding of the nature and advantages of this invention, as well as the preferred mode of use, reference should be made to the following detailed description read in conjunction with the accompanying drawings which are not to scale.
The following description is of the best embodiments presently contemplated for carrying out this invention. This description is made for the purpose of illustrating the general principles of this invention and is not meant to limit the inventive concepts claimed herein.
Referring now to
The magnetic reference layer 102 can be part of an anti-parallel magnetic pinning structure 112 that can include a magnetic keeper layer 114, and a non-magnetic, antiparallel coupling layer 116 located between the keeper layer 114 and reference layer 102. The antiparallel coupling layer 116 can be a material such as Ru and can be constructed to have a thickness such that it will ferromagnetically antiparallel couple the layers 114, 102. The antiparallel coupling between the layers 114, 102 pins the magnetization 108 of the reference layer 102 in a direction opposite to the direction of magnetization 118 of the keeper layer 114.
A seed layer 120 may be provided near the bottom of the memory element 100 to initiate a desired crystalline structure in the above deposited layers. A capping layer 122 may be provided near the top of the memory element 100 to protect the underlying layers during manufacture, such as during high temperature annealing and from exposure to ambient atmosphere. Also, electrodes 124, 126 may be provided at the top and bottom of the memory element 100. The electrodes 124, 126 may be constructed of a non-magnetic, electrically conductive material such as Ta, W, Cu and Al can provide electrical connection with circuitry 128 that can include a current source and can further include circuitry for reading an electrical resistance across the memory element 100.
The magnetic free layer 104 has a perpendicular magnetic anisotropy that causes the magnetization 110 of the free layer 104 to remain stable in one of two directions perpendicular to the plane of the free layer 104. In a write mode, the orientation of the magnetization 110 of the free layer 104 can be switched between these two directions by applying an electrical current through the memory element 100 from the circuitry 128. A current in one direction will cause the memory element to flip to a first orientation, and a current in an opposite direction will cause the magnetization to flip to a second, opposite direction. For example, if the magnetization 110 is initially oriented in a downward direction in
On the other hand, if the magnetization 110 of the free layer 104 is initially in an upward direction in
In order to assist the switching of the magnetization 110 of the free layer 104, the memory element 100 may include a spin polarization layer 130 formed above the free layer 104. The spin polarization layer can be separated from the free layer 104 by a coupling layer 132. The spin polarization layer 130 has a magnetic anisotropy that causes it to have a magnetization 134 with a primary component oriented in the in-plane direction (e.g. perpendicular to the magnetizations 110, 108 of the free and reference layers 104, 102. The magnetization 134, of the spin polarization layer 130 may either be fixed or can move in a precessional manner as shown in
The memory element 202 can have a structure such as the memory element 100 described above with reference to
Maintaining a desired crystal structure and thickness of the barrier layer 214 is important to maintaining good magnetic tunnel junction performance. However, it has been found that high temperature treatment processes necessary for the CMOS circuitry fabrication which are performed after formation of the magnetic memory element 202 can degrade the structure of the barrier layer 214 and, therefore, negatively affect memory element performance.
The nanofabrication of magnetic memory element pillars in magnetic memory arrays involves the use of back-end CMOS semiconductor circuitry fabrication technology. Part of this back-end-of-line CMOS processing requires a thermal treatment after the formation of the magnetic memory element pillars (e.g. 202). This thermal treatment can include treatment at temperatures of up to 400 degrees Celsius for an extended period of time.
Because this thermal annealing treatment is performed after the formation of the memory element pillars 202, the pillars and surrounding structure must be designed to withstand such thermal treatments. One challenge that arises as a result of the thermal annealing is the affect of such thermal treatment on the already formed barrier layer 214, especially with regard to the use of dielectric isolation layer structures at the side of the memory element. Materials such as silicon oxides (SiOx) and silicon nitrides (SiNx) are desirable materials for use in such isolation structure for electrically isolating pillar structures from one another, because they have good dielectric properties and good properties for chemical mechanical polishing (CMP), the use of which will be described in greater detail herein below. However, at such high temperatures Si from the SiOx or SiNx layers can diffuse into the barrier layer, greatly degrading the performance of the memory element by negatively affecting the quantum tunneling properties of the barrier layer 214 and also by creating shunting paths at the outer edges of the barrier layer 214 due to formation of conductive Si nanocrystal filaments in proximity of the barrier layer 214. This problem is further exacerbated by the fact that the milling process used to form the pillar structure forms a rough surface on the outer edge of the pillar structure. This rough edge forms nucleation points which encourage the formation of Si nanocrystals at the outer edge of the pillar structure. These nanocrystals can connect to each other and act as electrical shunts which lead to low device resistance and greatly reduced performance of the memory element. In addition, defects in the MgO barrier resulting from the presence of Si degrade the tunneling properties of the MgO barrier layer, substantially decreasing TMR performance.
A novel structure as described generally with reference to
The isolation structure 216 can further include one or more other types of dielectric layers formed over or beside the first layer 218, so that the first layer 218 separates these other layers from the pillar structure 202 and more importantly separates these other layers from the barrier layer 214. In the exemplary embodiment shown in
The first layer 218 can be constructed as a single layer or as a multi-layer structure and can be have a thickness of 1-5 nm. Preferably, the first layer 218 can be formed as a single layer of naturally oxidized or reactively oxidized Mg to form single MgO layer.
The memory element array 300 can be formed with an isolation structure 304 that includes first second and third layers 306, 308, 310. The first layer 306 is formed of a material that is the same as or similar to the material of the barrier layer 214 of the memory element pillar 202. For example, the barrier layer 214 can be formed of magnesium oxide and the first isolation layer 306 can be formed of magnesium oxide having an oxygen concentration that is within plus or minus 5 atomic percent of the magnesium oxide of the barrier layer 214. The first layer 306 has a tapered structure as shown in
In the exemplary embodiment described with reference to
The tapered shape of the first layer 306 is optimal for both facilitating manufacturing such as by providing optimal properties for chemical mechanical polishing (CMP) and also effectively preventing Si diffusion into the barrier layer 214. MgOx is not an optimal material for chemical mechanical polishing (a process which will be needed to form a planar upper surface on the memory element pillar structure), while silicon oxide (SiOx) responds well to chemical mechanical polishing and provides good process control for chemical mechanical polishing. Because the first layer 306 does not extend to the top of the pillar structure 302, there will be no MgO at this region to be subject to chemical mechanical polishing. This advantageously leaves the SiOx layer 308 and SiNx layer 310 to withstand the chemical mechanical polishing. However, because the layer 306 is present in the region adjacent to the barrier layer structure 214 it can provide very effective protection against Si diffusion into the barrier layer. This advantageously allows greatly improved diffusion barrier protection while eliminating any disadvantage of having the MgOx being subject chemical mechanical polishing.
With reference now to
With the mask 502 in place, a material removal process is performed to remove portions of the magnetic element material 406 that are not protected by the mask structure 502, leaving a structure as shown in
With reference now to
The first layer 702 can be deposited by one of several deposition techniques so as to form an oxide, such as MgOx. Since the layer 702 is preferably MgOx so as to match with the barrier layer (not shown), the deposition of the first layer 702 will be described as a process for depositing MgOx. One way to deposit a MgOx layer 702 is by a plasma vapor deposition (PVD) process in a deposition chamber using a target containing both Mg and O (e.g. a MgO target). In this deposition process Radio Frequency (RF) sputtering can be used by sputtering MgO directly from the MgO target. Alternatively, the deposition of the layer 702 can be performed using DC magnetron sputtering or radio frequency (RF) sputtering and can be deposited as a series of layers or as a single layer. Preferably, however, the layer 702 is deposited as a series of layers of Magnesium (Mg) using a Plasma Vapor Deposition (PVD) process by sputtering from Mg target and is then reactively (ROx) or naturally (NOx) oxidized until a desired oxygen content is achieved to effectively match stochimetric MgO for layer 702. This process allows the layer 702 to be more easily deposited to a desired thickness (preferably 1-5 nm) and also advantageously allows good control of the oxidation process. Again, this process could be performed so as to deposit the layer 702 as multiple oxide layers rather than a single layer.
After the first layer 702 has been deposited, second, third and fourth layers 704, 706, 708 are successively deposited over the first layer 702. The second layer 704, deposited directly over the first layer 702, can be silicon oxide (SiOx). The third layer 706 can be deposited as a dielectric layer that is resistant to chemical mechanical polishing (CMP) so as to make a good CMP stop layer. For example, the third layer 706 is preferably SiNx, which provides good dielectric properties and also functions as a good CMP stop layer. The fourth layer 708 is preferably formed of SiOx, which provides good properties for subsequent chemical mechanical polishing (CMP) such as good control of CMP material removal rate. The second, third and forth layers 704, 706, 708 can all be deposited by various conformal deposition processes and are preferably deposited by plasma-enhanced chemical vapor deposition (PECVD).
After the layers 702, 704, 706, 708 have been deposited, a chemical mechanical polishing (CMP) can be performed to planarize the structure. The CMP process is performed until the third layer 706 is reached. The layer 706 is used as a CMP stop layer (as discussed) because of its good resistance to removal by CMP. The fourth layer 708, which was included to facilitate the CMP process can be removed by the CMP, leaving a structure such as that shown in
With reference to
With reference to
With reference to
Then, an etching process is performed to etch back the first dielectric layer 1202. This etching process causes the first dielectric layer to form a tapered dielectric sidewall 1202 as shown in
With reference to
After the layers 1302, 1304, 1306 have been deposited, a chemical mechanical polishing process can be performed to planarize the structure, leaving a structure as shown in
With reference to
While various embodiments have been described above, it should be understood that they have been presented by way of example only and not limitation. Other embodiments falling within the scope of the invention may also become apparent to those skilled in the art. Thus, the breadth and scope of the inventions should not be limited by any of the above-described exemplary embodiments but should be defined only in accordance with the following claims and their equivalents.
