Claims
- 1. A method of making a guard-ring in a face of a body of semiconductor material, the guard ring substantially surrounding an array of transistors at said face to prevent unwanted carriers from entering the area of said array, comprising the steps of:
- forming a deep heavily-doped region of one conductivity type in said body of semiconductor material adjacent said face thereof; the semiconductor material contiguous to said deep heavily-doped region being much more lightly doped with impurity of said one type,
- and thereafter forming a shallow heavily-doped region of opposite conductivity type above said deep heavily-doped region to provide guard ring surrounding a cell array area of said face.
- 2. A method according to claim 1 wherein the body is P-, the deep region is P+, and the shallow region is N+.
- 3. A method according to claim 1 wherein the deep region is formed by implanting at high energy level to cause implant damage and locally lower the minority carrier lifetime in the body.
- 4. A method according to claim 2 including the steps of forming memory cells in said face on one side of the deep region and forming other circuitry in said face on the other side.
- 5. A method according to claim 4 wherein the deep region is formed in a ring completely surrounding said memory cells.
- 6. A method according to claim 4 wherein the memory cells include N-channel silicon-gate transistors and MOS capacitors.
Parent Case Info
This is a division of application Ser. No. 083,928 filed Oct. 11, 1979.
US Referenced Citations (6)
Divisions (1)
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Number |
Date |
Country |
Parent |
83928 |
Oct 1979 |
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