Patent Application
20110089525
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2008-16207 filed on Jan. 28, 2008, the entire contents of which are incorporated herein by reference.
The present invention relates to a manufacturing method for a semiconductor device, for example, using STI (Shallow Trench Isolation) for element isolation.
In recent years, with requirements of miniaturization and high functionality of electronic devices, STI has been used as an element isolation technique for improvement of device performance, such as miniaturization and higher performance.
Generally, STI is formed in the following way. First, a shallow trench is formed on a semiconductor substrate using a mask material such as a SiN film by RIE (Reactive Ion Etching) method. After an insulating material is embedded in the trench using HDP-CVD (High Density Plasma-Chemical Vapor Deposition) method, the trench is flattened using CMP (Chemical Mechanical Polishing) method. In addition, the mask material is selectively removed using hot phosphoric acid (H3PO4) solution to form STI. At this time, there is a height difference corresponding to the mask material between a formed STI surface and a semiconductor substrate surface.
Next, on the semiconductor substrate including the STI, a gate electrode material such as a polysilicon film and a gate side wall material such as a TEOS (Tetra Ethoxy Silane) film, a BSG film (boron-doped oxide film) and an SiN film are deposited and patterned to form a gate electrode. At this time, such materials remain on a STI side face at the height difference portion, which causes a low yield due to dust generation.
Accordingly, there has been known a method for forming a side face (height difference) of a protruding STI into a forward tapered shape to inhibit generation of etching residues during processing of a gate electrode or a gate side wall, as disclosed in claim 1 and a paragraph [0019] of Japanese Patent Application Laid-Open No. 2000-21967. However, processing of STI after removal of a mask material causes damage to a semiconductor substrate so that gate leak due to a crystalline defect may occur. Further, by only chamfering the side face, residues cannot be effectively removed.
According to an aspect of the present invention, there is provided a manufacturing method for a semiconductor device including: forming a trench on a semiconductor substrate with a first insulation film patterned on the semiconductor substrate as a mask; embedding a second insulation film in the trench; selectively removing an upper portion of the first insulation film to expose a part of a side face of the second insulation film; isotropically removing a part of the second insulation film; selectively removing a lower portion of the remaining first insulation film; further isotropically removing a part of the remaining second insulation film so that an upper face of the second insulation film is at a predetermined height from a surface of the semiconductor substrate, a taper having a minimum taper angle of 90° or more is formed on the side face of the second insulation film, and a STI is formed.
According to an aspect of the present invention, there is provided a semiconductor device including an active area formed on a semiconductor substrate, and a STI which isolates the active area and has an upper face protruding to a height of 22 to 50 nm from a surface of the semiconductor substrate and a side face having a taper of a minimum taper angle of 90° or more.
Reference will now be made in detail to the present embodiment of the invention, an example of which is illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawing to refer to the same or like parts.
The STI 11 is formed from, for example, a thermal oxide film 11a/a TEOS film 11b. A top face of the TEOS film 11b is protruding from a surface of the semiconductor substrate w and, on the side face of a protruding portion of the TEOS film lib, a taper 11c is formed. As illustrated in
In a region element-isolated by the STI 11, there is formed an active area 12 having source-drain regions and an LDD (Lightly Doped Drain) regions formed so as to sandwich a channel region in a well. On the active area 12, there is formed a gate electrode 13 including a polysilicon layer 13b formed on a gate insulation film 13a and a silicide layer (not illustrated) formed on the surface of the gate electrode 13. The gate electrode 13 has gate side walls including insulation films such as a TEOS film 14a and a SiN film 14b.
On these layers, an interlayer film 15 is formed and the source-drain regions and the gate electrode 13 are connected, through contacts 16 formed so as to penetrate through the interlayer film 15, to an upper-layer wiring 17 and an electrode (not illustrated) to configure MOSFET.
Such a semiconductor device is formed in the following way. First, as illustrated on a partial sectional view of a STI formation region in
With the resist pattern as a mask, the SiN film 21 is etched using the RIE (Reactive Ion Etching). Further, a STI trench 22 is formed when the semiconductor substrate w is etched down, for example, 300 nm, and the resist pattern is removed. In this state, the STI trench 22 has a little inclination, that is, a taper having an angle of less than 90° resulting from machinability of RIE.
As illustrated in
As illustrated in
As illustrated in
As illustrated in
In this state, for example, as illustrated in
Impurities are doped in the semiconductor substrate w to form an impurity diffusion region which is a P-type or N-type well channel region on the surface side of the semiconductor substrate w. After the surface of the semiconductor substrate w is preprocessed, an insulation film for a gate insulation film 13a is formed in the thickness of, for example, 1.3 nm. On the insulation film, a polysilicon film for a polysilicon layer 13b constituting the gate electrode 13 is formed in the thickness of, for example, 150 nm, using LPCVD method.
A resist film is applied onto a polysilicon film and a resist pattern is formed using the lithographic method. The polysilicon film is etched using the RIE method with the resist pattern as a mask. After etching, the resist pattern is removed to form the polysilicon layer 13b constituting a gate electrode 13. The exposed insulation film is wholly removed by wet etching to form the gate electrode 13.
Impurities are doped in the well to form a shallow impurity diffusion region. After the TEOS film is formed in the thickness of, for example, 20 nm using LPCVD method, a SiN film is formed in the thickness of, for example, 20 nm. Using RIE method, the SiN film is etched back until the polysilicon layer 13b is exposed. As described above, a gate side wall including the TEOS film 14a and the SiN film 14b is formed beside the gate electrode 13.
Impurities are doped in the well to form the active area 12 having a source-drain region and a LDD region. After the source-drain region and a surface of the polysilicon layer 13b are salicided, the interlayer film 15 is formed. The contact 16 is formed so as to penetrate through the interlayer film 15. In addition, the upper-layer wiring 17 and an electrode (not illustrated) are formed, and a MOSFET cell as illustrated in
By half etching the SiN film 21 in the MOSFET cell formed in this way, lower yield caused by dust generation resulting from etching residues can be inhibited without generation of etching residues to a STI side surface during processing of a gate electrode or gate side walls. In addition, damage to the semiconductor substrate w can be inhibited during tapering, thus obtaining satisfactory element characteristics.
Further, half etching using hot phosphoric acid used for removing a SiN film at the postprocess can be implemented, and a process can be easily added.
As described above, by only etching the STI side surface, a good side surface shape cannot be obtained and drawbacks such as generation of a constricted portion occur.
For example, in a case where a taper angle of the SiN film is 78°, when a height of STI is 35 nm, a required half-etching amount is approximately 40 nm. When the height of STI is less than 22 nm, generation of a constricted portion (a portion having a taper angle of less than 90°) can be inhibited without half etching. On the other hand, when the half-etching amount is less than 30 nm, dependence of generation of a constricted portion upon a half-etching amount is inhibited without depending upon a taper angle.
Accordingly, by the previously designed STI height and a taper angle of the SiN film changing with a process, the half-etching amount of the SiN film is adjusted as needed, thus obtaining good STI side surface shape. For example, when a height of STI required for device properties is 22 nm or more, more preferably 30 nm or more and a taper angle of SiN is 74° to 90° which is to be processed in ordinary RIE, it is sufficient to control the half-etching amount to be 30 nm or more.
Since tapering is performed by an isotropical etching manner, the height of STI is equal to or less than the thickness of the SiN film used as a mask. Accordingly, formation of a SiN film is required so as to obtain a film thickness in view of the half-etching amount. On the contrary, when the SiN film thickness is approximately 150 nm which is a mask film thickness in the ordinary process, the height of STI is preferably 50 nm or less to ensure adequate amount of half etching, thus improving shape controllability.
In the present embodiment, the SiN film is half-etched using hot phosphoric acid, which is not specially limited thereto, provided that a selective ratio of the SiN film to an insulation film such as a TEOS film embedded in the STI can be determined. For example, the half etching can employ CDE (Chemical Dry Etching) using CF4, N2, or C2.
In this case, an etching selection ratio of SiN to TEOS (SiO2) is approximately 2:1 and the TEOS film is etched concurrently with the half etching of the SiN film, but it is sufficient to adjust the etching amount of the TEOS film in the wet etching by BHF at the postprocess. In the use of CDE, etching speed and selective ratio change from those in the use of hot phosphoric acid and therefore the shoulder portion of STI is etched a little more and a taper angle of STI shape becomes larger than the present embodiment. When the CDE is used, since an etching process is a dry process, the endpoint of half etching can be easily controlled.
In the present embodiment, after the remaining lower portion 21′ of the SiN film is wholly removed by hot phosphoric acid, the shape is controlled using buffered hydrofluoric acid (BFH) prepared by blending hydrofluoric acid (HF) with ammonium fluoride (NH4F). The shape control of the side surface of STI may be implemented in fluorine pretreatment in forming a gate insulation film at the postprocess.
In the present embodiment, the SiN film is used as a mask material. However, a mask material is not particularly limited. For example, a material such as silicon carbide can be used. In that case, similarly, shape control of the side surface of the STI can be implemented by etching under such a condition where a selective ratio of the mask material to a component material of the STI can be determined.
Other embodiments of the invention will be apparent to those skilled in the art from consideration of the specification and practice of the invention disclosed herein. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the invention being indicated by the following claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2008-016207 | Jan 2008 | JP | national |
| Number | Date | Country | |
|---|---|---|---|
| Parent | 12359635 | Jan 2009 | US |
| Child | 12926905 | US |
