Method for forming silicon structures, such as upright gates or fins on a wafer substrate, particularly for use as a building block for semiconductor devices. The structures are smaller than can be resolved by conventional optical lithography. A plan of the area-wise dimensions of the fin or gate structure is mapped to a substrate as an ideal, Conductive and insulative layers are deposited onto the substrate and a work region that includes the desired structure is designed by photolithography. An opening is etched in the work region and a frame is created protective of the desired structure. Most of the frame is etched away except over the structure and then this portion is used to protect the structure so that remaining material can be removed until only the gate over the substrate remains. This process is carried out in many places over a wafer with the structures preferably aligned in rows and columns for making memory or logic arrays.
Description
BRIEF DESCRIPTION OF DRAWINGS
FIGS. 1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, and 23 are top plan views of manufacturing steps for devices of the present invention.
FIGS. 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, and 22 are side views of manufacturing steps for devices of the present invention.
Claims
1. The method of making a microminiature structure on a planar substrate comprising:
mapping a structure region of desired dimensions smaller than optical resolution from a plan onto a wafer substrate;providing selected structure material over a wafer substrate region that includes the mapped structure;protecting structure material over the mapped structure region with a mask that is larger in area-wise extent than the mapped structure reducing the area of the protected structure material to correspond to the structure area;removing unprotected structure material from the substrate; andremoving the mask, thereby exposing the structure material on the wafer substrate region as a structure smaller than optical resolution limits.
2. The method of claim 1 wherein said mask is a rectangular frame.
3. The method of claim 3 wherein the rectangular frame is defined by etching an opening in said mask.
4. The method of claim 1 further defined by simultaneously manufacturing a plurality of structures smaller than optical resolution limits.
5. The method of claim 4 wherein said structures are aligned in rows.
6. The method of claim 4 wherein said structures made of material selected from the group of amorphous silicon, polysilicon, and silicon.
7. The method of claim 4 wherein said wafer is doped on sides of the structures to form transistors.
8. The method of claim 5 wherein said structures cover the surface of a wafer.
9. A method of making a microminiature structure on a planar substrate comprising:
mapping a structure region from a plan onto a substrate, the mapped structure region having a length and width, the length being smaller than optical resolution limits;covering the substrate with a first layer of structure material;forming an optically resolved work region with a second layer over the first layer within a photoresist boundary that encloses the structure region;etching an opening in the work region, through the second layer;creating a frame, of second layer material around the opening an the work region covering the mapped structure region, the frame having a length dimension corresponding to the length of the structure region;protecting a portion of the frame corresponding to at least the length and width of the structure region;removing the unprotected portion of the frame leaving a protected frame portion over the mapped structure region;using the protected frame portion as a mask to protect the mapped structure region in the first layer as a structure, while removing remaining first layer material; andremoving all remaining frame portions to leave the mapped region as a structure in the first layer over the substrate.
10 . The method of claim 9 wherein said substrate is a silicon wafer with an insulative coating.
11. The method of clam 10 wherein the first layer is a conductive layer.
12. The method of claim 10 wherein the first layer is a polysilicon one layer.
13. The method of claim 9 wherein the protecting a portion of the frame corresponding to at least the length and width of the gate region is by photoresist.
14. The method of claim 9 wherein the second layer material is a polysilicon two layer.
15. The method of claim 9 wherein the second layer material is a nitride layer.
16. The method of claim 9 simultaneously replicated a plurality of times on the same substrate.
17. The method of claim 16 wherein replicated gate structures are aligned in rows.
18. The method of claim 16 wherein replicated gate structures are rows and columns.
19. The method of claim 9 wherein the frame is created by photolithographic patterning and etching.
20. The method of making polysilicon fins arrays on a wafer substrate comprising;
mapping rows of polysilicon fins having dimensions smaller than optical resolution limits onto a wafer, each fin separated from another by dimensions of an optically resolved work region;coating the wafer with a first layer of polysilicon;defining the work regions with a second layer over the first layer, each work region having a boundary that encloses a mapped fin;etching openings in the work region through the second layer to create frames;protecting a frame portion for each frame corresponding to at least one fin dimension;removing the unprotected portion of the frames leaving protected frame portions over the mapped fins;using the protected frame portions as a mask to protect the mapped fins in the first layer as polysilicon fins, while removing remaining first layer material; andremoving all remaining frame portions to leave polysilicon fins in the first layer over the substrate.
Patent Application
20070166971
