Patent Application
20130198578
1. Technical Field
Embodiments of the present disclosure relate generally to integrated circuit (IC) testing, and more specifically to techniques for maximizing re-use of external pins of an integrated circuit for testing.
2. Related Art
Integrated circuits (IC) typically need to be tested to uncover faults in circuitry within the ICs. For example, post-fabrication testing is usually performed on ICs. Typically, an IC is connected to an external tester via the external pins of the IC. The tester then generates test patterns, provided to the IC via the external pins. The response of one or more internal blocks or circuitry in the IC to the test patterns may be read back by the tester, also via the external pins. Any faults in the IC may be determined by the tester based on analysis of the response. The IC itself may be designed with circuitry for enabling such testing, and such design techniques that incorporate testability features in an IC are generally referred to as design for testability or DFT. An example type of test that may be performed on an IC is a scan-based test, well known in the relevant arts.
To minimize test cost (for example cost incurred in use of a tester) and/or test time, it may be desirable to test multiple ICs simultaneously, i.e., in parallel. Thus, a same test (i.e., with the same test patterns, etc) may be performed simultaneously on the multiple ICs (typically of the same type/functionality). The number of ICs that can be tested simultaneously is usually limited by the number of pins available on the tester used to perform the test. Thus, for any given number of tester pins, the number of ICs that can be tested simultaneously is increased if the number of test pins required per IC is smaller. To this end, an IC may be designed to enable a same external pin on the IC to be used as a test pin (i.e., to send or receive a test signal during testing) in addition to providing normal functionality, i.e., the external pin which provides normal functionality (i.e., carries the intended signal/s in normal functional mode of operation) is re-used as a test pin during testing. Such re-use of a pin also leads to lower packaging cost of the IC. It may be desirable to maximize the number of such pins for re-use during testing.
This summary is provided to comply with 37 C.F.R. §1.73, requiring a summary of the invention briefly indicating the nature and substance of the invention. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.
An integrated circuit (IC) comprising a plurality of external pins, a configuration logic, a test configuration register and a sequence detector. The plurality of external pins includes a first set of external pins. At least one external pin in the first set is coupled to receive, during a configuration phase, a first configuration signal used in configuring a circuit block internal to the IC for a test designed to uncover faults in the circuit block, but is coupled to receive a first test signal during the test. The configuration logic is designed to generate control data by decoding configuration signals received during the configuration phase, the control data being designed to configure the circuit block for the test. The first configuration signal is included in the configuration signals. The test configuration register is coupled to the configuration logic during the configuration phase to receive the control data. The test configuration register is designed to store and apply the control data during the test, but is decoupled from the configuration logic at the end of the configuration phase and prior to commencement of the test. The sequence detector is designed to detect a reset sequence signifying an end of the test, and to re-couple the test configuration register to the configuration logic in response to detecting the reset sequence. In an embodiment, the first set of external pins is connected to the JTAG terminals of a JTAG engine in the IC.
Several embodiments of the present disclosure are described below with reference to examples for illustration. It should be understood that numerous specific details, relationships, and methods are set forth to provide a full understanding of the embodiments. One skilled in the relevant art, however, will readily recognize that the techniques can be practiced without one or more of the specific details, or with other methods, etc.
Example embodiments will be described with reference to the accompanying drawings briefly described below.
The drawing in which an element first appears is indicated by the leftmost digit(s) in the corresponding reference number.
Various embodiments are described below with several examples for illustration.
1. Example Test Environment
As noted above, a same test procedure may simultaneously be applied on each of ICs 120-1 through 120-N, and ICs 120-1 through 120-N may be identical to each other. In general, it is desirable for reasons such as for example, cost of tester usage time, that the number of ICs tested simultaneously be maximized. Such a requirement is usually related to the number of pins on each IC (e.g., ICs 120-1 through 120-N) that are required to enable the test to be performed. Generally, lesser the number of pins (termed test pins for convenience) required to be ‘touched’ on each IC during testing, greater the number of ICs that can be tested simultaneously, given a total number of pins available on tester 110.
One technique that is used to minimize the number of test pins on an IC is to re-use some of the JTAG pins on an IC. As is well known in the relevant arts, JTAG refers to the Joint Test Action Group specification (standardized as the IEEE 1149.1 Standard) that specifies a Test Access Port and a Boundary-Scan Architecture for ICs for purposes such as for testing circuitry on a printed circuit board, in-circuit emulation and debugging, etc. JTAG specifies five signals, namely, TDI, TDO, TMS, TCK and TRST, and the specifications of these signals may be obtained from the IEEE 1149.1 standard.
As used herein, the term ‘JTAG pin’ refers to an external pin (of an IC) that is connected to a JTAG engine (in the IC) and serves to carry any of signals TDI, TDO, TMS, TCK or TRST as defined in the IEEE 1149.1 standard.
To minimize the number of test pins required for testing IC 120-1, some of IC pins 201 through 205 may additionally be connected to other circuitry (i.e., other than JTAG engine 210) within IC 120-1. As an example, pin 201 may be used via path 220 for connection to an input of a scan chain configured for a sequential scan test, and may thus serve as a ‘scan-in’ (SI) pin during the sequential scan test. Suitable circuitry (not shown in
It may be desirable to re-use all of pins 201 through 205 to serve as test pins (for testing of circuitry within IC 120-1), in addition to providing normal functionality as JTAG pins TDI, TDO, TMS, TCK and TRST.
2. Techniques To Re-Use JTAG Pins as Test Pins for IC Testing
Scan chain 355 represents a set of memory elements (e.g., flip-flops) contained in the functional portion of IC 120-1. The term ‘functional portion’ refers to circuitry within IC 120-1 that is designed to provide the intended function or operation of IC-120 in normal (functional mode) operation. For example, assuming IC 120-1 is a processor, the functional portion may include arithmetic logic units, registers, microcode sequencer, etc., that enable the processor to provide the corresponding processor functionality. As described below, sequential scan tests may be performed on scan chain 355, which may itself be formed (typically during a configuration phase) into a chain prior to such scan test. Memory 335 may also be considered as part of the functional portion of IC 120-1, and represents on-chip memory, which may be implemented in any suitable form, such as for example, static random access memory (SRAM).
In contrast, the circuits/blocks (except scan chain 355 and memory 335) shown in
External pin 201 is connected to the TDI (test data input) connection (311) of JTAG engine 210, and also to the input of DEMUX 325 via path 312. The connection of external pin 201 via path 312 to DEMUX 325 serves to provide the alternative functionality of external pin 201 as a test pin, as described below.
External pin 202 is connected to the output of MUX 345, whose inputs 341 and 313 (TDO) respective are the output of MUX 340 and the TDO (test data output) connection of JTAG engine 210. Thus, external pin 202 may serve as the TDO output of JTAG engine 210 or as a test pin, as described below.
External pin 203 is connected to the input of DEMUX 410, and to the TMS (test mode select) connection (via path 409) of JTAG engine 210. Thus, external pin 203 is designed to serve as the TMS input of JTAG engine 210, as well as a test pin via connection through DEMUX 410, as described below.
External pin 204 is connected to the input of DEMUX 420, and to the TCK (test clock) connection (via path 419) of JTAG engine 210. Thus, external pin 204 is designed to serve as the TMS input of JTAG engine 210, as well as a test pin via connection through DEMUX 410, as described below.
External pin 205 is connected to the input of DEMUX 440, and to the TRST (test reset) connection (via path 439) of JTAG engine 210. Thus, external pin 205 is designed to serve as the TRST input of JTAG engine 210, as well as a test pin via connection through DEMUX 440, as described below. In an embodiment, pin 205 and the TRST signal of JTAG engine 210 are not implemented.
The operation of the relevant blocks shown in
On reset of IC 120-1, pin 205 is maintained at logic one. As a result, the TRST input of JTAG engine 210 is at logic one, and JTAG mode is enabled. Signal 351 (Lock) is at logic zero, and gating logic 315 is enabled to forward signal 314 on path 316. MUX 345 forwards signal 313 (TDO) on pin 202. Tester 110 transmits configuration data on pin 201, with the configuration data designed to set IC 120-1 in sequential scan test mode. The configuration data are received by JTAG engine 210 via the TDI input 311. Tester 110 generates clock signals on pin 204, which are available on clock terminal TCK (419), to clock-in the configuration data. In addition, tester 110 may control the value of the signal on pin 203 to control the value of signal TMS (409). JTAG engine 210 forwards the configuration data on path 314 to configuration-and-gating logic 315.
Configuration-and-gating logic 315 decodes the configuration data received from JTAG engine 210, and generates corresponding control/configuration bits to set IC 120-1 in sequential scan test mode. The control/configuration bits include those required for creation of scan chains (e.g., such as that for ‘stitching’ the corresponding flip-flops to form scan chain 355), setting of the speed of the clock used for capture in scan testing, appropriate select signals for controlling the operation of components 325, 340, 410, 420 and 440, etc.
Configuration-and-gating logic 315 forwards the control/configuration bits on path 316 to test configuration register 320 for storage. The forwarding of the control/configuration bits on path 316 is enabled only if signal 351 (Lock) enables such forwarding. It is assumed that a logic zero value of signal 351 enables such forwarding, while a logic one value of signal 351 disables such forwarding. Following reset, signal 351 is at logic zero, and the control/configuration bits are forwarded to test configuration register 320 for storage as well as for applying the control/configuration bits to the corresponding signal lines (although not shown in the Figures).
Based on the configuration data received, configuration-and-gating logic 315 sets bit 321 to logic zero. As a result, MUX 340 forwards signal 356 (SO-1) on path 341, DEMUX 325 forwards signal 312 on path 326 (SI-1), DEMUX 410 forwards signal 203 (i.e., signal on pin 203) on path 411 (SE), DEMUX 420 forwards signal 204 on path 421 (SCLK), and DEMUX 440 forwards signal 205 on path 441 (SI-2). The configuration phase corresponding to sequential scan test is depicted in
In addition, at the end of the sequential scan test configuration (i.e., once the control/configuration bits corresponding to the sequential scan test have been set/applied) and prior to the start of the sequential scan test, configuration-and-gating logic 315 sets signal 322 to logic one. In response to signal 322 being logic one, JTAG lock register 350 sets signal 351 (Lock) to logic one. A logic one level of signal 351 (Lock) disables the outputs of configuration-and-gating logic 315 (e.g., signal 316) from being forwarded to test configuration register 320. Also, a logic one level of signal 351 selects signal 341 as the output of MUX 345 on pin 202. The sequential scan test configuration effects the following pin configurations:
Pin 201 is connected to the scan-in (input) path 326 (SI-1) of scan chain 355.
Pin 202 is connected to the scan-out (output) path 356 (SO-1) of scan chain 355.
Pin 203 is connected to the scan-enable path 411 (SE) of scan chain 355.
Pin 204 is connected to the scan-clock path 421 (SCLK) of scan chain 355.
Assuming that pin 205 and TRST connection of JTAG engine 210 are implemented, pin 205 is connected to the scan-in path 441 (SI-2) of another scan chain (not shown).
Sequential scan tests are then performed on scan chains such as scan chain 355. While only one scan chain 355 is shown in IC 120-1, more number of scan chains can be created in IC 120-1 with corresponding scan-in, scan-out, scan-clock and scan-enable connections via other pins of IC 120-1. Tester 110 may analyze the response bits corresponding to the scan tests to determine faults in the scan chains. The sequential scan test phase is depicted in
Due to the direct connection of pins 201, 203 and 204 to the TDI, TMS and TCK terminals respectively of JTAG engine 210, the bit values on these pins during the sequential scan tests will affect the state of JTAG engine 210 in a manner determined by the specific signal/bit values on these pins. As a result, the inputs (via path 314) to configuration-and-gating logic 315 and the response of configuration-and-gating logic 315 to such inputs may not be predictable. However, such unpredictable effects are not of concern since the inputs to test configuration register 320 via path 316 are disabled (due to signal 351 (Lock) being a logic one), and the configuration data stored in test configuration register 320 are not affected. Hence, the direct connection of pins 201, 203 and 204 to the TDI, TMS and TCK terminals of JTAG engine 210 do not affect the operations of the sequential scan tests.
At the end of the sequential scan tests, tester 110 generates, in interval t52-t53 (shown expanded in
Sequence detector 430 receives as signals 308, 309 and 311 (TDI) as inputs. Signal 308 indicates whether JTAG engine 210 is in Pause-IR state or not, while signal 309 indicates whether JTAG engine 210 is in Pause-DR state or not. On occurrence of the sequence (reset sequence) of
Pattern-1 and pattern-2 can be any pre-determined pattern known beforehand to sequence detector 430. It may be observed that the TDI connection (311) is directly connected to sequence detector 430. Since, the TDI path (311) will contain test data during the sequential scan tests, the specific patterns pattern-1 and pattern-2, as well as the overall sequence of
Following the completion of the sequence of
Configuration-and-gating logic 315 decodes the configuration data received from JTAG engine 210, and generates corresponding control/configuration bits to set IC 120-1 in memory test mode. The control/configuration bits or data include those required for enabling memory BIST (Built-in self test) controller 330 to perform the memory test, such as for example, the data width to be used in performing the test, the size of memory 335, etc. In addition, the configuration bits also enable appropriate select signals for controlling the operation of components 325, 340, 410, 420 and 440, as described below.
Based on the configuration data received, configuration-and-gating logic 315 sets bit 321 to logic one. As a result, MUX 340 forwards signal 334 (Pass/Fail) on path 341, DEMUX 325 forwards signal 312 on path 327, DEMUX 410 forwards signal 203 (i.e., signal on pin 203) on path 412 (ME), DEMUX 420 forwards signal 204 on path 422, and DEMUX 440 forwards signal 205 on path 442. Signals 327, 412 (ME) 422 (R/W) and 442, during the configuration phase for memory test are used to configure memory BIST controller 330 for the memory test. In some embodiments, signals 327, 412 (ME), 422 (R/W) and 442 are connected directly to memory BIST controller 330 (as shown in
At the end of the memory test configuration (i.e., once the control/configuration bits corresponding to the memory test have been set/applied) and prior to the start of the memory test, configuration-and-gating logic 315 sets signal 322 to logic one. In response to signal 322 being logic one, JTAG lock register 350 sets signal 351 (Lock) to logic one. A logic one level of signal 351 (Lock) disables the outputs of configuration-and-gating logic 315 from being forwarded to test configuration register 320. Also, a logic one level of signal 351 selects signal 341 as the output of MUX 345 on pin 202. The sequential scan test configuration effects the following pin configurations:
Pin 201 is connected to path 327.
Pin 202 is connected to path 334 (Pass/Fail).
Pin 203 is connected to path 412.
Pin 204 is connected to path 422.
Assuming that pin 205 and TRST connection of JTAG engine 210 are implemented, pin 205 is connected to path 442.
Memory tests are then performed on memory 335 by memory BIST controller 330. Typically, the memory tests include writing a know data pattern to a memory location in memory 335 and reading back the written data. A comparison of the written and read-back values can indicate potentials faults in memory 335. Paths 331, 332 and 333 respectively represent address, data and control paths connecting Memory BIST controller 330 and memory 335. The result (pass or fail) of the memory test are indicated by memory BIST controller 330 on path 334 (Pass/Fail), which is available on pin 202 and can be read by tester 110. The memory test phase is depicted in
At the end of the memory test at t55, tester 110 again generates the sequence of
Thus, it may be appreciated that in interval t50-t51, pins 201, 202, 203 and 204 serve as JTAG connections TDI, TDO, TMS, and TCK for configuring IC 120-1 for sequential scan tests, while in interval t51-t52 they serve as test pins to receive/send test signals corresponding to the sequential scan tests. Similarly, in interval t53-t54, pins 201, 202, 203 and 204 again serve as JTAG connections TDI, TDO, TMS, and TCK for configuring IC 120-1 for memory tests, while in interval t54-t55 they serve as test pins to receive/send test signals corresponding to the memory tests. Pin 205, if implemented, may be used in a similar manner during either of the two tests.
While only two tests (namely, sequential scan tests and memory tests) are described above, other tests may also be performed in the same manner. For example, once the sequence of
The issuing by tester 110 of the sequence of
While the description above is provided specifically with respect to re-using JTAG pins of an IC, it may be appreciated that the techniques can also be used in re-using pins that are used to connect non-functional signals of an IC, i.e., signals that are not associated with signals generated during the functional mode operation of the IC. The specific circuitry required to enable re-use of such pins may vary based on what circuit connections the pins normally provide. However, the above-described technique of using pins (e.g., ‘non-functional-mode’ pins such as JTAG pins TDI, TMS, etc.) to configure corresponding circuit portions for a test during a configuration phase, then re-using the pins as test pins (e.g., SI-1, SE, etc) while maintaining the ‘configured information’ intact (i.e., not affected by changes in signal values on the test pins during testing), followed by re-enabling of configuration of corresponding circuit portions for a next test enables reduction of pin count required for testing an IC.
Furthermore, more than two tests can be performed in succession (i.e., back-to-back) using the same set of pins (201-204 or 201-205 in the example of
Still further, each of pins 201-205 can be designed to serve additionally as functional pins as well, as shown in the example of
While in the illustrations of
While various embodiments of the present disclosure have been described above, it should be understood that they have been presented by way of example only, and not limitation. Thus, the breadth and scope of the present disclosure should not be limited by any of the above-described embodiments, but should be defined only in accordance with the following claims and their equivalents.
