Input/Output interfaces

Industry

CPC
G01R31/318572

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Parent Industries

GPHYSICS G01Measuring instruments G01RMEASURING ELECTRIC VARIABLES MEASURING MAGNETIC VARIABLES G01R31/00Arrangements for testing electric properties Arrangements for locating electric faults Arrangements for electrical testing characterised by what is being tested not provided for elsewhere

Current Industry

G01R31/318572Input/Output interfaces

Industries

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Patents Grantslast 30 patents

Information Patent Grant
Test access port with address and command capability
- Patent number 12,188,980
- Issue date Jan 7, 2025
- Texas Instruments Incorporated
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Grant
At-speed test access port operations
- Patent number 12,181,521
- Issue date Dec 31, 2024
- Texas Instruments Incorporated
- Lee D. Whetsel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Chip test circuit and circuit test method
- Patent number 12,181,519
- Issue date Dec 31, 2024
- Huawei Technologies Co., Ltd.
- Changming Cui
- G01 - MEASURING TESTING
Information Patent Grant
3D tap and scan port architectures
- Patent number 12,164,001
- Issue date Dec 10, 2024
- Texas Instruments Incorporated
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Grant
Commanded JTAG test access port operations
- Patent number 12,153,090
- Issue date Nov 26, 2024
- Texas Instruments Incorporated
- Lee D. Whetsel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
TVF transition coverage with self-test and production-test time red...
- Patent number 12,146,911
- Issue date Nov 19, 2024
- STMICROELECTRONICS INTERNATIONAL N.V.
- Venkata Narayanan Srinivasan
- G01 - MEASURING TESTING
Information Patent Grant
Selectable JTAG or trace access with data store and output
- Patent number 12,146,909
- Issue date Nov 19, 2024
- Texas Instruments Incorporated
- Lee D. Whetsel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cost-saving scheme for scan testing of 3D stack die
- Patent number 12,099,091
- Issue date Sep 24, 2024
- Advanced Micro Devices, Inc.
- Songgan Zang
- G01 - MEASURING TESTING
Information Patent Grant
Selectable JTAG or trace access with data store and output
- Patent number 12,092,687
- Issue date Sep 17, 2024
- Texas Instruments Incorporated
- Lee D. Whetsel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Scan test in a single-wire bus circuit
- Patent number 12,092,689
- Issue date Sep 17, 2024
- Qorvo US, Inc.
- Alexander Wayne Hietala
- G11 - INFORMATION STORAGE
Information Patent Grant
Wrapper cell design and built-in self-test architecture for 3DIC te...
- Patent number 12,066,490
- Issue date Aug 20, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd
- Anshuman Chandra
- G01 - MEASURING TESTING
Information Patent Grant
Test access port architecture to facilitate multiple testing modes
- Patent number 12,057,183
- Issue date Aug 6, 2024
- Micron Technology, Inc.
- Michael Richard Spica
- G11 - INFORMATION STORAGE
Information Patent Grant
Integrated test circuit, test assembly and method for testing an in...
- Patent number 12,055,587
- Issue date Aug 6, 2024
- Infineon Technologies AG
- Tobias Kilian
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Systems, methods, and devices for high-speed input/output margin te...
- Patent number 12,055,584
- Issue date Aug 6, 2024
- Tektronix, Inc.
- Daniel S. Froelich
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Addressable test access port
- Patent number 12,050,247
- Issue date Jul 30, 2024
- Texas Instruments Incorporated
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Grant
Integrated circuit die test architecture
- Patent number 12,025,649
- Issue date Jul 2, 2024
- Texas Instruments Incorporated
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Grant
Power-sensitive scan-chain testing
- Patent number 12,025,661
- Issue date Jul 2, 2024
- MARVELL ASIA PTE. LTD.
- Balaji Upputuri
- G01 - MEASURING TESTING
Information Patent Grant
Process for scan chain in a memory
- Patent number 11,971,448
- Issue date Apr 30, 2024
- Ceremorphic, Inc.
- Robert F. Wiser
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Dummy dual in-line memory module (DIMM) testing system based on bou...
- Patent number 11,965,931
- Issue date Apr 23, 2024
- INVENTEC (PUDONG) TECHNOLOGY CORPORATION
- Yuan Sang
- G01 - MEASURING TESTING
Information Patent Grant
Hold time improved low area flip-flop architecture
- Patent number 11,946,973
- Issue date Apr 2, 2024
- Texas Instruments Incorporated
- Arnab Khawas
- G01 - MEASURING TESTING
Information Patent Grant
FPGA chip with protected JTAG interface
- Patent number 11,941,133
- Issue date Mar 26, 2024
- Hewlett Packard Enterprise Development LP
- Siung Siew Liew
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Built-in self-test for die-to-die physical interfaces
- Patent number 11,940,491
- Issue date Mar 26, 2024
- Apple Inc.
- Fabien S. Faure
- G01 - MEASURING TESTING
Information Patent Grant
Apparatus and system for debugging solid-state disk (SSD) device
- Patent number 11,933,847
- Issue date Mar 19, 2024
- Silicon Motion, Inc.
- Han-Chih Tsai
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems, methods, and devices for high-speed input/output margin te...
- Patent number 11,927,627
- Issue date Mar 12, 2024
- Tektronix, Inc.
- Daniel S. Froelich
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for schedule-based I/O multiplexing for integrate...
- Patent number 11,927,630
- Issue date Mar 12, 2024
- MARVELL ASIA PTE. LTD.
- Sounil Biswas
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
DIMM slot test system without series connection of test board throu...
- Patent number 11,927,632
- Issue date Mar 12, 2024
- INVENTEC (PUDONG) TECHNOLOGY CORPORATION
- Chang-Qing Mu
- G01 - MEASURING TESTING
Information Patent Grant
Early detection of quality control test failures for manufacturing...
- Patent number 11,892,507
- Issue date Feb 6, 2024
- Exfo Inc.
- Jonathan Plante
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Scan testing using scan frames with embedded commands
- Patent number 11,879,941
- Issue date Jan 23, 2024
- Texas Instruments Incorporated
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Grant
Integrated circuit chip testing interface with reduced signal wires
- Patent number 11,860,228
- Issue date Jan 2, 2024
- Xilinx, Inc.
- Albert Shih-Huai Lin
- G01 - MEASURING TESTING
Information Patent Grant
Stimulated circuits and fault testing methods
- Patent number 11,852,685
- Issue date Dec 26, 2023
- Hamilton Sundstrand Corporation
- Christopher Blazer
- G01 - MEASURING TESTING

Patents Applicationslast 30 patents

Information Patent Application
ERROR RATE MEASUREMENT APPARATUS AND ERROR RATE MEASUREMENT METHOD
- Publication number 20250020718
- Publication date Jan 16, 2025
- Anritsu Corporation
- Hironori YOSHIOKA
- G01 - MEASURING TESTING
Information Patent Application
SCAN-TESTABLE ELECTRONIC CIRCUIT AND CORRESPONDING METHOD OF TESTIN...
- Publication number 20240426908
- Publication date Dec 26, 2024
- STMicroelectronics International N.V.
- Andrea Floridia
- G01 - MEASURING TESTING
Information Patent Application
TVF TRANSITION COVERAGE WITH SELF-TEST AND PRODUCTION-TEST TIME RED...
- Publication number 20240402249
- Publication date Dec 5, 2024
- STMicroelectronics International N.V.
- Venkata Narayanan Srinivasan
- G01 - MEASURING TESTING
Information Patent Application
SELECTABLE JTAG OR TRACE ACCESS WITH DATA STORE AND OUTPUT
- Publication number 20240402247
- Publication date Dec 5, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ADDRESSABLE TEST ACCESS PORT
- Publication number 20240385244
- Publication date Nov 21, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Application
Wrapper Cell Design and Built-In Self-Test Architecture for 3DIC Te...
- Publication number 20240361385
- Publication date Oct 31, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Anshuman Chandra
- G01 - MEASURING TESTING
Information Patent Application
Segmented Boundary Scan Chain Testing
- Publication number 20240353490
- Publication date Oct 24, 2024
- Ee Mei Ooi
- G01 - MEASURING TESTING
Information Patent Application
INTEGRATED CIRCUIT DIE TEST ARCHITECTURE
- Publication number 20240345154
- Publication date Oct 17, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Application
SCAN TEST IN A SINGLE-WIRE BUS CIRCUIT
- Publication number 20240345162
- Publication date Oct 17, 2024
- Qorvo US, Inc.
- Alexander Wayne Hietala
- G11 - INFORMATION STORAGE
Information Patent Application
TESTING SYSTEM AND TESTING METHOD
- Publication number 20240345164
- Publication date Oct 17, 2024
- ASMedia Technology Inc.
- Te-Ming Kung
- G01 - MEASURING TESTING
Information Patent Application
Configurable Storage Circuits And Methods
- Publication number 20240337692
- Publication date Oct 10, 2024
- Intel Corporation
- Rajiv Kumar
- G01 - MEASURING TESTING
Information Patent Application
SCAN CHAIN SECURITY CIRCUIT AND DRIVING METHOD THEREOF
- Publication number 20240280633
- Publication date Aug 22, 2024
- UIF (UNIVERSITY INDUSTRY FOUNDATION), YONSEI UNIVERSITY
- Sungho KANG
- G01 - MEASURING TESTING
Information Patent Application
SAVING AND RESTORING SCAN STATES
- Publication number 20240230758
- Publication date Jul 11, 2024
- Atmosic Technologies, Inc.
- Mohsen Shaaban
- G01 - MEASURING TESTING
Information Patent Application
HOLD TIME IMPROVED LOW AREA FLIP-FLOP ARCHITECTURE
- Publication number 20240210472
- Publication date Jun 27, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Arnab Khawas
- G01 - MEASURING TESTING
Information Patent Application
AT-SPEED TEST ACCESS PORT OPERATIONS
- Publication number 20240061038
- Publication date Feb 22, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PERFORMING SCAN DATA TRANSFER INSIDE MULTI-DIE PACKAGE WITH SERDES...
- Publication number 20240027525
- Publication date Jan 25, 2024
- ADVANCED MICRO DEVICES, INC.
- AHMET TOKUZ
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SELECTABLE JTAG OR TRACE ACCESS WITH DATA STORE AND OUTPUT
- Publication number 20240019489
- Publication date Jan 18, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
COST-SAVING SCHEME FOR SCAN TESTING OF 3D STACK DIE
- Publication number 20240019493
- Publication date Jan 18, 2024
- ADVANCED MICRO DEVICES, INC.
- SongGan Zang
- G01 - MEASURING TESTING
Information Patent Application
SCAN TESTING USING SCAN FRAMES WITH EMBEDDED COMMANDS
- Publication number 20240012050
- Publication date Jan 11, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Application
METHOD AND SYSTEM FOR TESTING SEMICONDUCTOR CIRCUITS
- Publication number 20240003972
- Publication date Jan 4, 2024
- Ampere Computing LLC
- Kha NGUYEN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
3D TAP & SCAN PORT ARCHITECTURES
- Publication number 20230417831
- Publication date Dec 28, 2023
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Application
INTERFACE/UNICAST FOR TEST CONTENT, FIRMWARE, AND SOFTWARE DELIVERY
- Publication number 20230408581
- Publication date Dec 21, 2023
- Intel Corporation
- Rakesh Kandula
- G01 - MEASURING TESTING
Information Patent Application
ADDRESSABLE TEST ACCESS PORT
- Publication number 20230400513
- Publication date Dec 14, 2023
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Application
SCAN TESTING USING SCAN FRAMES WITH EMBEDDED COMMANDS
- Publication number 20230384376
- Publication date Nov 30, 2023
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Application
Built-in Self-Test for Die-to-Die Physical Interfaces
- Publication number 20230384377
- Publication date Nov 30, 2023
- Apple Inc.
- Fabien S. Faure
- G01 - MEASURING TESTING
Information Patent Application
INTEGRATED CIRCUIT CHIP TESTING INTERFACE WITH REDUCED SIGNAL WIRES
- Publication number 20230366929
- Publication date Nov 16, 2023
- Xilinx, Inc.
- Albert Shih-Huai LIN
- G01 - MEASURING TESTING
Information Patent Application
MANAGING DATA PROTECTION SETTINGS FOR AN ELECTRONIC CONTROL UNIT
- Publication number 20230368588
- Publication date Nov 16, 2023
- Rivian IP Holdings, LLC
- Jack Austin Doan
- B60 - VEHICLES IN GENERAL
Information Patent Application
INTEGRATED CIRCUIT DIE TEST ARCHITECTURE
- Publication number 20230366920
- Publication date Nov 16, 2023
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Application
Wrapper Cell Design and Built-In Self-Test Architecture for 3DIC Te...
- Publication number 20230366930
- Publication date Nov 16, 2023
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Anshuman Chandra
- G01 - MEASURING TESTING
Information Patent Application
TEST ACCESS PORT WITH ADDRESS AND COMMAND CAPABILITY
- Publication number 20230333159
- Publication date Oct 19, 2023
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G01 - MEASURING TESTING

Input/Output interfaces

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Test access port with address and command capability

At-speed test access port operations

Chip test circuit and circuit test method

3D tap and scan port architectures

Commanded JTAG test access port operations

TVF transition coverage with self-test and production-test time red...

Selectable JTAG or trace access with data store and output

Cost-saving scheme for scan testing of 3D stack die

Selectable JTAG or trace access with data store and output

Scan test in a single-wire bus circuit

Wrapper cell design and built-in self-test architecture for 3DIC te...

Test access port architecture to facilitate multiple testing modes

Integrated test circuit, test assembly and method for testing an in...

Systems, methods, and devices for high-speed input/output margin te...

Addressable test access port

Integrated circuit die test architecture

Power-sensitive scan-chain testing

Process for scan chain in a memory

Dummy dual in-line memory module (DIMM) testing system based on bou...

Hold time improved low area flip-flop architecture

FPGA chip with protected JTAG interface

Built-in self-test for die-to-die physical interfaces

Apparatus and system for debugging solid-state disk (SSD) device

Systems, methods, and devices for high-speed input/output margin te...

System and method for schedule-based I/O multiplexing for integrate...

DIMM slot test system without series connection of test board throu...

Early detection of quality control test failures for manufacturing...

Scan testing using scan frames with embedded commands

Integrated circuit chip testing interface with reduced signal wires

Stimulated circuits and fault testing methods

Patents Applicationslast 30 patents

ERROR RATE MEASUREMENT APPARATUS AND ERROR RATE MEASUREMENT METHOD

SCAN-TESTABLE ELECTRONIC CIRCUIT AND CORRESPONDING METHOD OF TESTIN...

TVF TRANSITION COVERAGE WITH SELF-TEST AND PRODUCTION-TEST TIME RED...

SELECTABLE JTAG OR TRACE ACCESS WITH DATA STORE AND OUTPUT

ADDRESSABLE TEST ACCESS PORT

Wrapper Cell Design and Built-In Self-Test Architecture for 3DIC Te...

Segmented Boundary Scan Chain Testing

INTEGRATED CIRCUIT DIE TEST ARCHITECTURE

SCAN TEST IN A SINGLE-WIRE BUS CIRCUIT

TESTING SYSTEM AND TESTING METHOD

Configurable Storage Circuits And Methods

SCAN CHAIN SECURITY CIRCUIT AND DRIVING METHOD THEREOF

SAVING AND RESTORING SCAN STATES

HOLD TIME IMPROVED LOW AREA FLIP-FLOP ARCHITECTURE

AT-SPEED TEST ACCESS PORT OPERATIONS

PERFORMING SCAN DATA TRANSFER INSIDE MULTI-DIE PACKAGE WITH SERDES...

SELECTABLE JTAG OR TRACE ACCESS WITH DATA STORE AND OUTPUT

COST-SAVING SCHEME FOR SCAN TESTING OF 3D STACK DIE

SCAN TESTING USING SCAN FRAMES WITH EMBEDDED COMMANDS

METHOD AND SYSTEM FOR TESTING SEMICONDUCTOR CIRCUITS

3D TAP & SCAN PORT ARCHITECTURES

INTERFACE/UNICAST FOR TEST CONTENT, FIRMWARE, AND SOFTWARE DELIVERY

ADDRESSABLE TEST ACCESS PORT

SCAN TESTING USING SCAN FRAMES WITH EMBEDDED COMMANDS

Built-in Self-Test for Die-to-Die Physical Interfaces

INTEGRATED CIRCUIT CHIP TESTING INTERFACE WITH REDUCED SIGNAL WIRES

MANAGING DATA PROTECTION SETTINGS FOR AN ELECTRONIC CONTROL UNIT

INTEGRATED CIRCUIT DIE TEST ARCHITECTURE

Wrapper Cell Design and Built-In Self-Test Architecture for 3DIC Te...

TEST ACCESS PORT WITH ADDRESS AND COMMAND CAPABILITY