Maximum density interconnections for large scale integrated circuits

Abstract

A microelectronic integrated circuit having first and second levels of thin-film metallization separated by an insulation layer is provided with a system for electrical interconnections between metallization levels, at selected locations, without requiring extra spacing between metal paths, in either the first or second levels. Maximum circuit density is thereby permitted, with no restriction on the placement of interconnection vias. Circuit layout is greatly simplified because all metal paths have uniform widths and minimum spacings, achieved with the use of vias that are "oversized" in both the transverse and longitudinal directions. Consequently, it is required that second level metal differ in composition from first level metal, and be patterned with an etchant that does not attack first level metal.

Description

Claims

1. A semiconductor device, including a double level metal interconnect system having a surface insulator on the semiconductor; and an inter-level insulator between metal levels, wherein the device surface insulator embodies a via etch stop layer, the first level metal is an adherent metal of a high conductivity and not appreciably attacked by aluminum etchants; the inter-level insulator is silicon dioxide; the apertures in the inter-level insulator have longitudinal and transverse dimensions which exceed the width of the first and second level metal leads by at least 10% of the space between adjacent leads, the second level interconnect is aluminum, and the spacing between leads is substantially the same at all locations on the device.

2. A device as claimed in 1 wherein the first level metal is PtSi covered by a layer of a refractory metal barrier comprising a, Ti:W mixture and by a layer of Al doped with 1.5 to 2.5% Cu, and the second level metal is Ti:W mixture covered by a layer of Al.

3. A device as in claim 2 wherein the second level metal is Ti:W covered by Au, Ti:W covered by Ag, or TI:W covered by Palladium.

4. A device as in claimed in 2 wherein the refractory metal barrier is Ni, Cr, W, Ti, Ta, or Vanadium.

5. A device as in claim 1 wherein the first level metal is silicon (1-2%) doped Aluminum and the 2nd level metal is selected from Ti:W covered by Au, Ti:W covered by Ag, and Ti:W covered by Pd.

6. A double level interconnect system as claimed in 1 and the first level interconnect is polysilicon and the second level interconnect is pure aluminum or silicon and /or 1.5-2.5% copper doped aluminum.

7. A double level interconnect system as claimed in claims 1, 2, 3, 4, 5 or 6 wherein the interlevel insulator is a high temperature chemical vapor deposited silicon dioxide, or a sputtered quartz, or plasma vapor deposited silicon nitride, or any combination of these.

8. A double level interconnect system as claimed in 6 wherein the inter level insulator is a chemical vapor deposited silicon dioxide deposited at temperatures in excess of 500.degree. C.