Claims
- 1. A method of erasing a Flash EEPROM memory cell device, wherein said Flash EEPROM memory cell comprises:a semiconductor substrate; a tunneling oxide layer overlying said semiconductor substrate; a floating gate overlying said tunneling oxide; an interpoly oxide overlying said floating gate; a control gate overlying said interpoly oxide; a shallow and abrupt drain junction within said semiconductor substrate adjacent to said tunneling oxide layer; an angled pocket junction lying within said semiconductor substrate adjacent to said drain junction and counter-doped to said drain junction; and a deeper and less abrupt source junction lying within said semiconductor substrate; wherein said method of erasing said Flash EEPROM cell comprises the steps of: applying a voltage to said source junction of said cell to effect a low positive bias above a common ground reference; applying a voltage to said control gate of said cell to effect a low negative bias below said common ground reference; applying a voltage to said substrate of said cell to effect a low negative bias below said common ground reference; floating said drain junction of said cell; and discharging said floating gate of said cell by back bias hot hole injection sufficiently to erase said cell.
- 2. The method according to claim 1 wherein said step of applying a voltage to said control gate comprises a voltage of between about −3 volts and −5 volts.
- 3. The method according to claim 1 wherein said step of applying a voltage to said substrate comprises a voltage of about and −2 volts.
- 4. The method according to claim 1 wherein said step of applying a voltage to said source junction comprises a voltage of between about 3 volts and 5 volts.
- 5. The method according to claims wherein said tunneling oxide layer is formed to a thickness of between about 80 Angstroms and 120 Angstroms.
- 6. The method according to claim 1 wherein said ions implanted to form drain junctions comprise one of the group of: arsenic and antimony.
- 7. The method according to claim 1 wherein said ions implanted to form angled pocket junctions comprise boron.
Parent Case Info
This is a division of patent application Ser. No. 09/465,227, filing date Dec. 17, 1999, now U.S. Pat. No. 6,518,122 assigned to the same assignee as the present inventions
US Referenced Citations (25)