The present invention relates to a memory cell and methods of manufacturing thereof.
There is a limit in scaling conventional NAND-type nonvolatile flash memory devices beyond 50 nm, due to factors such as loss in floating gate capacitance coupling efficiency, data retention and reliability.
There are SONOS (silicon oxide nitride oxide silicon) structures, which are used because they are less sensitive to capacitive coupling issues and utilize thinner gate stacks, while there are FinFET (fin structure field effect transistors) structures that offer excellent electrostatic control of a short-channel body.
For instance, a conventional semiconductor device has a twin nanowire channel structure formed on a mounting surface of a silicon substrate, where both the nanowires are spaced laterally apart on the mounting surface. A gate region is formed above the mounting surface and around the exposed surfaces of the nanowires adjacent to the portions of the nanowires on the silicon substrate mounting surface.
However, the nanowire arrangement of the known semiconductor device occupies larger surface area on the mounting surface of the silicon substrate. Additionally, it would also be advantageous to provide a memory device with faster programming/erasing speeds, a wide memory window and stable data retention capability.
In an embodiment of the invention, there is provided a memory cell including: a first wire shaped channel structure; and a charge trapping structure surrounding the perimeter surface of the first wire shaped channel structure, the charge trapping structure including two charge trapping partial structures, wherein each charge trapping partial structure is formed of a different material capable of storing electrical charges.
In an embodiment of the invention, there is provided a method of forming a memory cell including the steps of forming a first wire shaped channel structure; and forming a charge trapping structure surrounding the perimeter surface of the first wire shaped channel structure, the charge trapping structure including two charge trapping partial structures, wherein each charge trapping partial structure is formed of a different material capable of storing electrical charges.
In an embodiment of the invention, there is provided a method of forming a memory cell, the method including the steps of: forming from a single conducting layer a first wire shaped channel structure and a second wire shaped channel structure; and forming a gate region around the perimeter surface of the first wire shaped channel structure and the perimeter surface of the second wire shaped channel structure; wherein the second wire shaped channel structure is spaced a greater distance from a mounting surface of the gate region than the distance the first wire shaped channel structure is spaced from the mounting surface of the gate region.
In the drawings, like reference characters generally refer to the same parts throughout the different views. The drawings are not necessarily to scale, emphasis instead generally being placed upon illustrating the principles of the invention. In the following description, various embodiments of the invention are described with reference to the following drawings, in which:
Exemplary embodiments of a semiconductor memory cell are described in detail below with reference to the accompanying figures. It will be appreciated that the exemplary embodiments described below can be modified in various aspects without changing the essence of the invention.
In the embodiment of the invention shown in
The charge trapping structure 104 surrounds the perimeter surface of the first wire shaped channel structure 110, where the first tunneling layer 102 surrounds the perimeter surface of the first wire shaped channel structure 110 so that the first tunneling layer 102 is disposed between the perimeter surface of the first wire shaped channel structure 110 and the charge trapping structure 104.
The charge trapping structure 104 includes two charge trapping partial structures 104a and 104b, wherein each charge trapping partial structure 104a and 104b is formed of a different material capable of storing electrical charges. The two charge trapping partial structures 104a and 104b may respectively be a first charge trapping layer 104a surrounding the perimeter surface of the first tunneling layer 102; and one or more first nanocrystals 104b surrounding the perimeter surface of the first charge trapping layer 104a.
The gate region 108 surrounds the perimeter surface of the charge trapping structure 104, where the first blocking structure 106 is disposed between the first charge trapping layer 104a and the gate region 108 on portions of the first charge trapping layer 104a not in contact with the one or more first nanocrystals 104b.
It will be appreciated that the first wire shaped channel structure 110 connects the source and drain regions (not shown, but compare both source region 304 and drain region 306 in
Having thus provided a Gate-All-Around (GAA) structure for the gate region 108 facilitates further device scalability of the memory cell, compared to current floating gate memory cells, as the GAA structure offers better electrostatic control of the shorter channel body in the first wire shaped channel structure 110. Additionally, the charge trapping structure 104 of the first charge trapping layer 104a and the one or more first nanocrystals 104b acts as a form of trap layer engineering (TLE) to provide a charge storage medium, where the one or more first nanocrystals 104b provide further charge trapping performance enhancement by increasing the memory window provided by the first charge trapping layer 104a. The collective structure 140 (the first wire shaped channel structure 110; the tunneling layer 102; the charge trapping structure 104; and the first blocking structure 106), together with the gate region 108 form a GAA vertically stacked memory cell (compare memory cell 300 of
In the embodiment of the invention shown in
The charge trapping structure 154 surrounds the perimeter surface of the first wire shaped channel structure 160, where the first tunneling layer 152 surrounds the perimeter surface of the first wire shaped channel structure 160 so that the first tunneling layer 152 is disposed between the perimeter surface of the first wire shaped channel structure 160 and the charge trapping structure 154.
The charge trapping structure 154 includes two charge trapping partial structures 154a and 154b, wherein each charge trapping partial structure 154a and 154b is formed of a different material capable of storing electrical charges. The two charge trapping partial structures 154a and 154b may respectively be a first charge trapping layer 154a surrounding the perimeter surface of the first tunneling layer 152; and one or more first nanocrystals 154b embedded in the first charge trapping layer 154a.
When using silicon for the one or more embedded first nanocrystals 154b, then a silicon-rich silicon nitride layer 154a may have to be used, where embedding may be performed at a temperature of about 1000° C.
The gate region 158 surrounds the perimeter surface of the charge trapping structure 154 so that the charge trapping structure 154 is disposed between the first tunneling layer 152 and the gate region 158.
Similar to the embodiment of the invention shown in
The charge trapping structure 204 surrounds the perimeter surface of the first wire shaped channel structure 210, where the first tunneling layer 202 surrounds the perimeter surface of the first wire shaped channel structure 210 so that the first tunneling layer 202 is disposed between the perimeter surface of the first wire shaped channel structure 210 and the charge trapping structure 204.
The charge trapping structure 204 includes two charge trapping partial structures 204a and 204b, wherein each charge trapping partial structure 204a and 204b is formed of a different material capable of storing electrical charges. The two charge trapping partial structures 204a and 204b are respectively a first charge trapping layer 204a surrounding the perimeter surface of the first tunneling layer 202; and one or more first nanocrystals 204b surrounding the perimeter surface of the first charge trapping layer 204a.
Additionally, the memory cell 300 (
The further charge trapping structure 224 surrounds the perimeter surface of the second wire shaped channel structure 220, where the second tunneling layer 222 surrounds the perimeter surface of the second wire shaped channel structure 220 so that the second tunneling layer 222 is disposed between the perimeter surface of the second wire shaped channel structure 220 and the further charge trapping structure 224.
The further charge trapping structure 224 includes two further charge trapping partial structures 224a and 224b, wherein each further charge trapping partial structure 224a and 224b is formed of a different material capable of storing electrical charges. The two charge trapping partial structures 224a and 224b may respectively be a second charge trapping layer 224a surrounding the perimeter surface of the second tunneling layer 222; and one or more second nanocrystals 224b surrounding the perimeter surface of the second charge trapping layer 224a.
The gate region 208 surrounds the perimeter surface of the charge trapping structure 204 and the perimeter surface of the further charge trapping structure 224. The first blocking structure 206 is disposed between the first charge trapping layer 204a and the gate region 208 on portions of the first charge trapping layer 204a not in contact with the one or more first nanocrystals 204b. Similarly, the second blocking structure 226 is disposed between the second charge trapping layer 224a and the gate region 208 on portions of the second charge trapping layer 224a not in contact with the one or more second nanocrystals 224b. The second wire shaped channel structure 220 is spaced a greater distance from a mounting surface 208a of the gate region 208 than the distance the first wire shaped channel structure 210 is spaced from the mounting surface 208a of the gate region 208.
Longitudinal axes (i.e. axes moving directly into the plane of the paper) of the first wire shaped channel structure 210 and the second wire shaped channel structure 220 may be substantially parallel with the mounting surface 208a of the gate region 208. Further, the longitudinal axes of the first wire shaped channel structure 210 and the second wire shaped channel structure 220 may be substantially perpendicular to an axis 208y normal to the mounting surface 208a of the gate region 208. In this manner, the first wire shaped channel structure 210 and the second wire shaped channel structure 220 are arranged to form a vertical stack with respect to the mounting surface 208a of the gate region 208. By arranging the wire shaped channel structures 210 and 220 in a vertically stacked orientation, the wire shaped channel structures 210 and 220 will have less “foot print” on the corresponding mounting surface of a silicon substrate (see mounting surface 302a of support substrate 302 of
It will be appreciated that the first wire shaped channel structure 210 and the second wire shaped channel structure 220 connect the source region 304 (
Having thus provided a Gate-All-Around (GAA) structure for the gate region 208 facilitates further device scalability of the memory cell 300 (
Similar to the embodiment of the invention shown in
The charge trapping structure 254 surrounds the perimeter surface of the first wire shaped channel structure 251, where the first tunneling layer 252 surrounds the perimeter surface of the first wire shaped channel structure 251 so that the first tunneling layer 252 is disposed between the perimeter surface of the first wire shaped channel structure 251 and the charge trapping structure 254.
The charge trapping structure 254 includes two charge trapping partial structures 254a and 254b, wherein each charge trapping partial structure 254a and 254b is formed of a different material capable of storing electrical charges. The two charge trapping partial structures 254a and 254b may respectively be a first charge trapping layer 254a surrounding the perimeter surface of the first tunneling layer 252; and one or more first nanocrystals 254b embedded in the first charge trapping layer 254a.
When using silicon for the one or more embedded first nanocrystals 254b, then a silicon-rich silicon nitride layer 254a may have to be used, where embedding may be performed at a temperature of about 1000° C.
Additionally, the memory cell includes a second wire shaped channel structure 281, a second tunneling layer 282 and a further charge trapping structure 284.
The further charge trapping structure 284 surrounds the perimeter surface of the second wire shaped channel structure 281, where the second tunneling layer 282 surrounds the perimeter surface of the second wire shaped channel structure 281 so that the second tunneling layer 282 is disposed between the perimeter surface of the second wire shaped channel structure 281 and the further charge trapping structure 284.
The further charge trapping structure 284 includes two further charge trapping partial structures 284a and 284b, wherein each further charge trapping partial structure 284a and 284b is formed of a different material capable of storing electrical charges. The two further charge trapping partial structures 284a and 284b may respectively be a second charge trapping layer 284a surrounding the perimeter surface of the second tunneling layer 282; and one or more second nanocrystals 284b embedded in the second charge trapping layer 284a.
When using silicon for the one or more embedded second nanocrystals 284b, then a silicon-rich silicon nitride layer 284a may have to be used, where embedding may be performed at a temperature of about 1000° C.
The gate region 258 surrounds the perimeter surface of the charge trapping structure 254 and the perimeter surface of the further charge trapping structure 284. In this manner, the charge trapping structure 254 is disposed between the first tunneling layer 251 and the gate region 258, while the further charge trapping structure 284 is disposed between the second tunneling layer 282 and the gate region 258.
In the embodiments of the invention, the first wire shaped channel structure (110, 210), the second wire shaped channel structure (220), or both the wire shaped channel structures are nanowires.
By using wire shaped channel structures in the embodiments of the invention, a better electrical equivalent oxide thickness (EOT), εox, is obtained for the same physical thickness, Tox, of a planar shaped channel structure.
For the planar shaped channel structure, capacitance, Cox, is determined by the equation:
C
ox=εox/Tox;
There is no field enhancement effect.
On the other hand, for a circular channel structure 280, cross section shown in
q=CoxΔV
it will be appreciated that a higher Cox will be obtained in the circular channel structure 280 due to the greater potential charge Q generated for the same voltage, ΔV, applied to the planar device. In this regard, a smaller circular channel structure can be employed to achieve the same results of a larger planar channel, i.e. reduction in the EOT of the circular channel structure 280 is possible by thinning the inner channel 270.
For the embodiments of the invention, any one or more of a group of conductive materials of poly-silicon, tantalum nitride, titanium nitride, hafnium nitride, aluminum and tungsten may respectively be used for the gate regions (108, 158, 208 and 258). To achieve an n-type memory cell for the embodiments of the invention, the gate regions (108, 158, 208 and 258) may respectively be doped with any one or more of a group of n-type dopants consisting of phosphorus, arsenic and antimony. On the other hand, to achieve a p-type memory cell for the embodiments of the invention, the gate regions (108, 158, 208 and 258) may be doped with any one or more of a group of p-type dopants consisting of boron, aluminum, gallium and indium. Any one or more of a group consisting of silicon and germanium may be used for both the first wire shaped channel structure (110, 160, 210 and 251) and the second wire shaped channel structure (220, 281). For the embodiments of the invention, any dielectric material may be used, for example silicon dioxide (SiO2), for both the first tunneling layer (102, 152, 202 and 252) and the second tunneling layer (222, 282). For the embodiments of the invention, any one or more of a group of high dielectric materials of silicon nitride (Si3N4), hafnium dioxide (HfO2) and aluminum oxide (Al2O3) may respectively be used for both the first charge trapping layer (104a, 154a, 204a and 254a) and the second charge trapping layer (224a, 284a) while any one or more of a group of metals of silicon nanocrystals (Si—NC), germanium nanocrystals and tungsten nanocrystals may respectively be used for both the one or more first nanocrystals (104a, 154a, 204b and 284b) and the one or more second nanocrystals (224b, 284b). For the embodiments of the invention, SiO2 may respectively be used for both the first blocking structure (106, 206) and the second blocking structure 226. To form an ONO (oxide nitride oxide) structure, SiO2, Si3N4 and SiO2 may be respectively used for the first tunneling layer (102, 202), the first/second charge trapping layer (104a/204a, 224a) and the the second tunneling layer (222). It will also be appreciated that in the embodiments of the invention, other materials with conduction and valence bands that are lower than the respective tunneling layer and the blocking structure can be used for the charge trapping layers. For instance, when SiO2 is used for both the the first tunneling layer (102, 152, 202 and 252) and the the second tunneling layer (222, 282), materials such as HfO2 and Al2O3 may be used, where HfO2 and Al2O3 have smaller bandgap energy, but have a better trap charging capability than SiO2
Returning to the embodiment of the invention shown in
The memory cell 300 includes a support substrate 302 formed of buried oxide (BOX), a source region 304, a drain region 306, the first and the second TLE SONOS structures 240 and 260, and a gate structure 308 that includes the gate region 208 (
The source region 304 and the drain region 306 are spaced apart from each other on a portion of a mounting surface 302a of the support substrate 302, where the source region 304 and the drain region 306 are both in contact with the support substrate 302.
The first TLE SONOS structure 240 connects the source region 304 and the drain region 306 together, so that one end of the first wire shaped channel structure 210 is integral with the source region 304, while an opposite end of the first wire shaped channel structure 210 is integral with the drain region 306. The second TLE SONOS structure 260 also connects the source region 304 and the drain region 306 together, so that one end of the second wire shaped channel structure 220 is integral with the source region 304, while an opposite end of the second wire shaped channel structure 220 is integral with the drain region 306.
In this manner the first wire shaped channel structure 210 and the second wire shaped channel structure 220 establish an electrical connection between the source region 304 and the drain region 306, to provide a channel for charge carriers flowing between the source 304 and the drain 306 regions.
It will be appreciated that the mounting surface 208a (
There is a gap 320 between the source region 304 surface and the respective gate structure 308 surface that is opposite to the source region 304. Similarly, there is a gap 322 between the drain region 306 surface and the respective gate structure 308 surface that is opposite to the drain region 306.
As the respective ends of the first wire shaped channel structure 210 and the second wire shaped channel structure 220 are integral with the source region 304 and the drain region 306, any one or more of a group consisting of silicon and germanium is used for both the source region 304 and the drain region 306. Also, as the gate structure 308 includes the gate region 208 (
The fabrication starts with a silicon-on-insulator (SOI) wafer 400 as a starting substrate in
The SOI wafer 400 includes a single conducting layer 402 separated vertically from a bulk support substrate 406 by a buried oxide (BOX) insulating layer 404. The BOX layer 404 electrically isolates the single conducting layer 402 from the bulk support substrate 406 and also acts as a support substrate to the single conducting layer 402. The SOI wafer 400 may be fabricated by any standard techniques, such as wafer bonding or a separation by implantation of oxygen (SIMOX) technique.
The single conducting layer 402 may typically be either silicon and/or germanium from an 8′ wafer, and is around 120 nm thick. However, other semiconductor materials including, but not limited to, poly-silicon and gallium arsenide may be used. The BOX layer 404 may typically be SiO2 but may be formed from any suitable insulating materials including, but not limited to, tetraethylorthosilicate (TEOS), Silane (SiH4), silicon nitride (Si3N4) or silicon carbide (SiC). The BOX layer 404 is about 1500 Angstrom thick but is not so limited. The bulk support substrate 406 may be formed from any suitable semiconductor materials including, but not limited to Si, sapphire, polysilicon, silicon dioxide (SiO2) or silicon nitride (Si3N4).
A photoresist layer 408 is applied or coated onto the top surface of the single conducting layer 402. The photoresist layer 408 has a fin structure 412 including a fin portion 414 arranged in between two supporting portions 416, where the fin structure 412 may be manufactured by standard photolithography techniques, for example 248 nm krypton fluoride (KrF) lithography. Alternating-Phase-Shift mask (AltPSM) may be used to trim the narrow fin portion 414 to obtain a fin portion width 414w of from about 40 to about 200 nm. Consequently, the shape and size of the first wire shaped channel structure 210 (refer
Subsequently, using the photoresist layer 408 as a mask, portions of the single conducting layer 402 not covered by the mask are etched away using phase shift mask lithography leaving behind a patterned single conducting layer 402b with a fin structure 422 (
After forming the patterned single conducting layer 402b, the photoresist layer 408 is removed or stripped away by a photoresist stripper (PRS) to produce the structure 410 shown in
A mask (not shown) is placed onto the upper surface 402bu of the fin structure 422, followed by a self limiting oxidation process of the masked patterned single conducting layer 402b carried out at 850° C. in dry O2 for 4 hrs. During the oxidation process, there is stress build up in the inner portion of the fin structure 422, which retards the oxidation rate of the inner portion. As the oxidation proceeds with thicker oxide being formed on the outer porter of the fin structure 422, the inner portion of the fin structure 422 will be oxidized at a slower rate than the outer portion structure. This retarded oxidation behavior will help to control the process at which the first wire shaped channel structure 210 and the second wire shaped channel structure 220 are formed and prevents entire oxidation of the first wire shaped channel structure 210 and the second wire shaped channel structure 220. As the upper surface 402bu of the fin structure 422 is masked, it is mainly the exposed portion 402be of the patterned single conducting layer 402b fin portion 424 that is subject to the oxidation process.
The exposed portion 402be of the fin portion 424 may be oxidised in dry O2 for around 4 hours at about 875° C. The structure 410 may then be treated to a solution of diluted HF so that the first wire shaped channel structure 210 and the second wire shaped channel structure 220, in the form of two vertically stacked Si nanowires, are released from the oxidised fin portion 424, as shown in
It will be appreciated that the formation of the twin nanowire structure from only the single conducting layer 402 provides for less complicated fabrication as opposed to forming the twin nanowire structure from a multi-layered substrate.
After the first wire shaped channel structure 210 and the second wire shaped channel structure 220 are formed, tunneling oxide layers and charge trapping structures are respectively deposited as shown in
Referring to FIGS. 4D(I) and 4D(II), the first tunneling layer 202; the second tunneling layer 222; and a third tunneling layer 432 are respectively deposited, at for example a current rating of about 45A and a temperature of about 720° C. using silane (SiH4) and nitrogen dioxide (NO2), around the perimeter surface of the first wire shaped channel structure 210; the perimeter surface of the second wire shaped channel structure 220; and the top surfaces of the support portion 426a. The first tunneling layer 202, the second tunneling layer 222, and the third tunneling layer 432 may be in the form of a thin film of SiO2 having a common thickness 202t, 222t and 432t of from about 3.0 to about 10 nm. It will be appreciated that the exact thickness of the tunneling layers may be determined by the specific programming/erasing voltage application. Lower voltages require thinner tunneling oxide.
Subsequent to the tunneling layer deposition, the first charge trapping layer 204a; the second charge trapping layer 224a; and a third charge trapping layer 434a are respectively deposited, at for example a current rating of for example around 45A at around 720° C. using dichlorosilane (DCS), around the perimeter surface of the first tunneling layer 202; the perimeter surface of the second tunneling layer 222; and the surface of the third tunneling layer 432. The first charge trapping layer 204a, the second charge trapping layer 224a; and the third charge trapping layer 434a may be in the form of Si3N4 having a common thickness 204at, 224at and 434at of from about 3 to about 30 nm. It will be appreciated that the thickness of the charge trapping layers determines the charge trapping efficiency of the memory cell and in turn the programming/erasing data rate. While having a thicker trapping layers allows for more charges to be stored, this increases the overall thickness of the memory cell and also the degree of voltage coupling between the gate region 208 [refer FIG. 4E(I)] surface and the first/second tunneling layers (202, 222).
Finally, the one or more first nanocrystals 204b; the one or more second nanocrystals 224b; and one or more third nanocrystals 434b are respectively deposited around the first charge trapping layer 204a, the second charge trapping layer 224a; and the third charge trapping layer 434a. The first charge trapping layer 204a and the one or more first nanocrystals 204b are also termed as two charge trapping partial structures of the charge trapping layer 204, where the charge trapping layer surrounds the perimeter surface of the first tunneling layer 202. The second charge trapping layer 224a and the one or more second nanocrystals 224b are also termed as two further charge trapping partial structures of the further charge trapping layer 224, where the further charge trapping layer surrounds the perimeter surface of the second tunneling layer 222.
The deposition of the tunneling layers, the charge trapping layer and the one or more nanocrystals may be performed under low pressure chemical vapour deposition (LPCVD), where the silicon nanocrystals may be formed by decomposing silane, SiH4 into Si and hydrogen H2 gas. The decomposition may be performed in a furnace using 100-200 cm3/min SiH4 flow at around 550 to 600° C.
In another embodiment (compare
Returning to the fabrication of the memory cell 300 (
Referring to FIG. 4E(I), the first blocking structure 206 is deposited on portions of the first charge trapping layer 204a not in contact with the one or more first nanocrystals 204b. Simultaneously, the second blocking structure 226 is deposited on portions of the second charge trapping layer 224a not in contact with the one or more second nanocrystals 224b. Deposition of the first blocking structure 206 and the second blocking structure 226 may be at for example a current rating of about 45A and a temperature of about 720° C. using silane (SiH4) and nitrogen dioxide (NO2). The first blocking structure 206 and the second blocking structure 226 may be in the form of a layer of SiO2 having a common thickness 206t and 226t of around 8 nm. Considering that the equivalent oxide thickness of silicon nitride, εSiN is around 7, the equivalent oxide thickness (EOT) of the ONO (the first/second tunneling layers 202/222, the first/second charge trapping layers 204a/224a and the first/second blocking structures 206/226) stacks 440 and 442 is from about 100 to about 200 nm.
Subsequently, the gate region 208 is deposited around the perimeter surfaces of the first blocking structure 206 and the second blocking structure 226 to form the Gate-All-Around (GAA) structure 308. In this manner, the first blocking structure 206 is formed between the first charge trapping layer 204a and the gate region 208, while the second blocking structure 226 is formed between the second charge trapping layer 224a and the gate region 208. The gate region 208 may be in the form of polysilicon having thickness 208t of from about 80 to about 200 nm. It will be appreciated that if too thin a polysilicon layer is formed, dopants will penetrate beyond the desired depth of the gate region 208 during the subsequent dopant stage (refer
The deposition of the blocking structures and the gate region may be performed under physical vapour deposition (PVD). However, in using PVD to deposit the gate region 208, uneven step-coverage in the form of undesirable shadow effects can occur leading to a non-uniform film formed around the the perimeter surfaces of the first blocking structure 206 and the second blocking structure 226. As a substitute, it will be appreciated that atomic layer deposition (ALD) using titanium nitride may be used.
Ion-implantation 480 using, for example phosphorus of concentration around 4×1015 cm−2 and at a doping energy level of around 30 keV and at a temperature of around 1000° C. for a duration of around 5 s, defines the source region 304, the drain region 306 and a gate region in the gate structure 308. Standard metallization and sintering (not shown), at a temperature of around 420° C. using 10% hydrogen gas (H2) concentration for a duration of around 30 min, may then be performed to form contact points for peripheral electronic devices (not shown) to access the memory cell 300.
In stage 502, the VST-Si nanowire structure (the first wire shaped channel structure 210 [
In stage 504, ONO structure (tunneling layer/charge trapping layer/blocking structure) in accordance to the description with reference to
Gate electrode deposition occurs in stage 506 in accordance to the description with reference to
Subsequently, gate patterning and etching occur in stage 508.
Finally and in accordance to the description with reference to
Broadly, the fabrication process of
In stage 552, the first wire shaped channel structure 210 [FIG. 4C(I)] and the second wire shaped channel structure 220 [FIG. 4C(I)] are formed from the single conducting layer 402 (
In stage 554, the gate region 208 [FIG. 4E(I)] is formed around the perimeter surface of the first wire shaped channel structure 210 and the perimeter surface of the second wire shaped channel structure 220.
In the stages 552 and 554, the fabrication is done so that the second wire shaped channel structure 220 is spaced a greater distance from the mounting surface 208a
[FIG. 4E(I)] of the gate region 208 than the distance the first wire shaped channel structure 210 is spaced from the mounting surface 208a of the gate region 208.
Similarly, to fabricate the memory cell of an embodiment of the invention, a flow chart 600, shown in
In stage 602, the first wire shaped channel structure 110 (
In stage 604, the charge trapping structure 104 (
Programming characteristics for the 5 nm and the 8 nm diameter nanowire devices are respectively shown in
Faster P/E speed is obtained for the nanowire with diameter of 5 nm. It is observed that faster P/E speed can be achieved up to a threshold voltage, ΔVth=3.2 V at Vp=11 V within 1 μs and at Vc=−10 V within 1 ms. The 5 nm diameter nanowire is faster from the scaling of the channel body into a smaller dimension, wherein the width of potential well in the nanowire channel is reduced. The charges being injected in the 5 nm diameter nanowire channel are pushed closer to the interface, further facilitating carrier efficiency in the TLE SONOS nanowire structure.
Also, Vth saturation becomes significant when large erasing voltages are applied in SONOS devices, because gate electrons injection neutralizes holes tunneling into the nitride charge trapping layer. However, Vth saturation is mitigated in erasure operations for TLE SONOS structures. This may be due to the reason that the Si—NC captures more holes during carrier tunneling from the substrate, for the same voltage value where erasure is performed in the non-TLE SONOS structure. Mitigated Vth saturation in a TLE SONOS structure is advantageous for widening A Vth during the erase cycle.
Both the TLE SONOS and the non-TLE SONOS devices display good memory retention properties as Δ Vth is well maintained up to approximately 104s with negligible observed memory window degradation. The good memory retention is partially due to the relatively thick blocking oxide present in both the TLE SONOS and the non-TLE SONOS devices. Another reason is the lower possibility of stored charges tunneling back to the channel due to the lifted, higher level ground state energy. Advantageously, the TLE SONOS memory cell shows improved operating speeds without compromising on memory retention capability.
For the results shown in
The above results discussed with reference to
While embodiments of the invention have been particularly shown and described with reference to specific embodiments, it should be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the invention as defined by the appended claims. The scope of the invention is thus indicated by the appended claims and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced.
Filing Document | Filing Date | Country | Kind | 371c Date |
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PCT/SG07/00421 | 12/7/2007 | WO | 00 | 9/28/2010 |