Patent Application
20080084757
Features and advantages of the invention may be readily appreciated by persons skilled in the art from the following detailed description of exemplary embodiments thereof, as illustrated in the accompanying drawings, in which:
In the following detailed description and in the several figures of the drawings, like elements are identified with like reference numerals.
In an exemplary embodiment, the sense amplifier 2 may sense a programming state (for example programmed or erased) of the memory cells 4. The sense amplifier 2 may provide, e.g., generate, a data signal 14, for example a voltage, representative of the programming state of a sensed memory cell 4. The processor 7 may include programming 13, such as software or firmware, for controlling the sense amplifier 2 to sense particular memory cells 4 and for processing the data signals 14 provided by the sense amplifier 2. The processor 7 may generate binary data 15 representative of the programmed state of the memory cell or cells 4 sensed.
A wordline 9a may be coupled to the gate of each memory cell 4a and 4b to be sensed. The memory cells' source sides S (in the case of drain-side sensing, drain side D in the case of source-side sensing) may be coupled to the sense amplifier 2 for sensing via bitlines 11a and 11b via select (top) transistors 17.
In an exemplary embodiment, currents Ia and Ib may be created, the current magnitudes corresponding to a programmed or erased state of the memory cells 4a and 4b. The currents Ia and Ib may combine to be sensed as one current I(a+b). In an exemplary embodiment, the magnitude of the current I(a+b) may correspond to the programmed state of the plurality 12 of memory cells 4, e.g. to the programmed state of memory cells 4a and 4b.
In an exemplary embodiment, the number of programmed or erased states available in a plurality 12 of memory cells 4 may depend, at least in part, on the maximum current window available for each individual cell 4. The window may be the desired difference between the target current range of one memory state (programmed or erased) and of a neighboring memory state.
In an exemplary embodiment, the size of the window 20 may be fixed by the process to avoid over-programmed cells or over-erased cells. The window 20 may depend, for example, on the total current that may be stored in the particular physical design of the memory cells and the differentiation possible between two states based on the sensing circuitry, sensing voltages and other process parameters and physical limitations. In an exemplary embodiment, the maximum one-cell window and/or the sizes of windows for a system may be determined by the maximum number of erase/program cycles, and/or by the system performance with respect to, e.g., erase time, program time, current consumption during algorithms, voltages in the system, and/or by the array effect.
In an exemplary embodiment, each memory cell sensed individually may store one data bit. Sensing each memory cell individually, however, may be subject to a so-called “neighbor effect,” in which current may be leaked from a memory cell to a neighboring memory cell during the sensing process, due at least in part to the voltage difference across the neighbor cell. The loss of current may result in inaccurate reading of data stored in the memory. Sensing more than one memory cell at a time, however, may provide a larger maximum current window, which may permit the storing and sensing of more than one data bit simultaneously.
In an exemplary embodiment, the process may permit setting the current window 22 between states at about 13 μA. In an exemplary embodiment, the maximum window 21 may permit up to 2×n, for example four, different programming states (P1, P2, E1 and E2). In an exemplary embodiment, we may refer to these states as P1, P2, E1 and E2 where P1 is a first programmed stated, P2 a second programmed state, E1 a first erased state and E2 a second erased state. For comparison,
Referring again to
In an exemplary embodiment, sensing a plurality (for example two) of memory cells at a time may provide some compensation for current losses due to the so-called “neighbor effect.” The “neighbor effect” may occur in other embodiments when a single memory cell is sensed. Current may leak through a neighboring cell when the bitline is charged for sensing.
In some embodiments, the “neighbor effect” may be compensated for, at least in part, by sensing two memory cells simultaneously but while storing only one information bit in the simultaneously sensed pair of memory cells. Storing only one information bit using two memory cells, however, may result in lower efficiency in using the memory array. Storing and sensing more than one information bit in a plurality of memory cells to be sensed simultaneously may compensate, at least in part, for the so-called “neighbor effect,” while providing increased efficiency in using the physical space of an array to store information.
In other embodiments, the “neighbor effect” may be compensated for by using a residual discharge/charge. In other words, the neighbor cells may be biased to the same level of the cell being sensed at least for the side used to sense the cell current. The use of a residual discharge/charge may incur costs of increased power consumption (because all of the global bitlines must be discharged/charged and discharging/charging the global bitline previously used) and access time (for example, because the operation may be performed before each read operation and must be well done).
Exemplary embodiments allow for canceling at least partially disturbance(s) coming from one or more neighbor cells. While in conventional memory cell arrays, expensive sequences (with respect to time and/or current) have to be performed before starting the read phase, this is not required anymore using exemplary embodiments of the invention.
While the foregoing is directed to exemplary embodiments of the present disclosure, other and further embodiments of the disclosure may be devised without departing from the basic scope thereof.
