Patent Application
20060203559
1. Field of the Invention
The present invention relates to memory devices having a preset configuration with respect to the number of operable data output ports.
2. Description of the Related Art
Memory devices such as dynamic random access memories (DRAMs) are sold in different quality grades, e.g., a high quality grade and a low quality grade. High quality memory devices are delivered to key customers and low quality memory devices are delivered to secondary markets and are often used for standard PC applications.
Moreover, memory devices such as DRAMs are offered in different I/O configurations, i.e., with a different number of data input and output ports. Most memory devices therefore have one of an ×4, ×8 or ×16 configuration, describing the number of data input/output ports. An ×4 organization, which means the memory device has only four data input/output ports, is typically used for server units as they require extremely high memory densities which are best achieved by the ×4 memory device configuration.
Usually, the layout of a memory device is fixed and the organization (e.g., ×4, ×8 or ×16 configuration) is typically defined by one of the last memory manufacturing steps (e.g., by providing a metal option, a laser fusing option or a bond option) before the final packaging. After the packaging, the set configuration is fixed and cannot be changed.
Particularly for memory devices with an ×4 configuration which are classified in a low quality grade, an issue exists since there is no need in the market for such low quality grade memory devices of such configuration. Because server units require server applications memory devices with high quality grades, low quality memory devices with an ×4 configuration cannot be utilized in such applications. As there is no other application for memory devices with ×4 configuration, such memory devices with a low quality grade are practically unmarketable.
Therefore, there is a need for a method to adapt memory devices according to market needs even after the memory devices have been packaged.
One aspect of the present invention provides a memory device which can be adapted even after packaging to meet the market needs with respect to its configuration and/or quality classification.
According to one embodiment of the present invention, a memory device is provided comprising a plurality of data output ports, a plurality of internal data lines, a switching unit which is operable, depending on an operational mode, either to connect a first number of the internal data lines to a first number of the plurality of data output ports in a first operational mode or to connect a second number of the internal data lines to a second number of the plurality of data output ports in a second operational mode, wherein the first number is different from the second number (e.g. smaller); and a mode selector unit which is connected to the switching unit to set the operational mode of the switching unit, wherein the mode selector unit includes a programmable storage unit for writing mode data after packaging and wherein the operational mode is determined depending on the mode data.
The memory device according to one embodiment of the present invention has the advantage, that it comprises a storage unit which can be programmed from outside of the memory device and allows for the changing of the configuration of the memory device after packaging with respect to the number of data input/output ports the memory device is operated with. This allows for the adapting of the memory device to the actual market needs if the I/O configuration-quality grade combination is actually not marketable. Since many memory devices have the same package and package bonding for several configurations (e.g., an ×4 and ×8 configuration of a memory device are identical in package and bonding), the present invention provides the possibility of reconfiguring an ×4 memory device into an ×8 memory device by means of a storage unit which is externally programmable even after packaging.
The programmable storage unit may comprise an electrical fuse element which is electrically programmable and which is adapted to store either a first mode data or a second mode data. The electrical programming may be performed by applying programming voltages and currents to respective ports of the memory device.
The programmable storage unit may comprise a configuration setting unit which is settable before packaging and which is adapted to provide either a first mode data or a second mode data.
In one embodiment, the fixed mode setting unit includes at least one of a laser fuse element, a bond option structure and a metal option structure in the memory device layout.
According to one embodiment of the present invention, the configuration setting unit and the electrical fuse element are coupled to a logic circuit which is adapted to generate an operational mode signal indicating the operational mode, wherein the operational mode signal determines the first operational mode if the configuration setting unit has stored the first mode data and the electric fuse element has stored the first mode data, and wherein the operational mode signal determines the second operational mode if the configuration setting unit or the electrical fuse element has stored the second mode data.
In one embodiment, the data output ports of the first number of data output ports are comprised in (or comprise a portion of) the data output ports of the second number of data output ports.
In one embodiment, the first number of data output ports equals 4, and the second number of data output ports equals 8.
So that the manner in which the above recited features of the present invention can be understood in detail, a more particular description of the invention, briefly summarized above, may be had by reference to embodiments, some of which are illustrated in the appended drawings. It is to be noted, however, that the appended drawings illustrate only typical embodiments of this invention and are therefore not to be considered limiting of its scope, for the invention may admit to other equally effective embodiments.
Embodiments of the present invention are not only related to this package type but describe a general approach which can be applied to all types of memory device packages, such as TSOP (Thin Small Outline Package), FBGA (Fine Pitch Ball Grid Array), TFBGA (Thin Fine Pitch Ball Grid Array), etc.
The bonding scheme shown in
After the packaging of the memory circuit chip 1 into the package 2 to obtain a memory device, a classification is performed. The packaged memory devices are divided up into at least a high quality grade and a low quality grade according to the classification step. Depending on the configuration of the memory device, there may be less or more need for memory devices of a specific quality grade in the market. As the quality grade of the memory device cannot be influenced after the final packaging, the number of high or low quality grades of a memory device of a specific configuration type is not known in advance prior to the classification step. Therefore, with conventional memory devices, responding to market requirements is not possible.
In
Each of the drivers 8 and each of the multiplexers 7 are controlled by the same control signal CS which defines the configuration of the data input/output ports of the memory device. The control signal determines whether the memory device is configured as an ×4 configuration memory device or an ×8 configuration memory device.
For example, with the control signal CS at a Low-level, the multiplexers 7 connect one of a first group 61 of the internal data lines with the respective data contact pad 4, respectively, and the drivers 8 are switched off to disconnect the remaining contact pads from the internal data lines. With the control signal CS at a High-level, the respective drivers 8 are switched on so that they connect one of the first group 61 of the internal data lines to the respective data contact pad 4, and the multiplexers 4 are switched so that they connect one of a second group 62 of the internal data lines, e.g., the respective data line pair which is more distanced from the contact pad line than the first group 61 of the internal data lines. Thus, if the control signal CS is at a Low-level, only four of the data contact pads 4 are connected to the respective internal data lines, and if the control signal CS is at a High-level, all eight internal data lines 6 are connected to their respective contact pads 4.
In conventional memory devices, the control signal CS is either hardwired set to a fixed potential, set by programming a laser fuse by means of a laser cutting process or set by an additional bond pad, resulting in that the control signal may not be set after packaging. According to one embodiment of the present invention, a mode selector unit 10 is provided on the memory circuit chip 1 which generates the control signal CS.
In the laser fuse element 11, for example, first mode data are stored if an ×8 configuration is to be preset, and second mode data are stored if an ×4 configuration is to be preset. The first mode data is indicated as a Low-level at the output of the laser fuse element 11, and the second mode data is indicated by a High-level at the output of the laser fuse element 11. A first mode data stored in the electrical fuse latch 15 indicates that the configuration preset of the laser fuse element should be valid, and a second mode data stored in the electrical fuse latch 15 indicates that the settings in the laser fuse elements 11 should be overrun and that an ×8 configuration should be set.
The laser fuse element 11 and the electrical fuse element 14 have permanently stored data. During chip power-up, the information in the laser fuse 13 and the information of the electrical fuse 16 is read out and stored in the respective fuse latch 12, 15.
Implementation of embodiments of the present invention is not restricted to the mode selector unit according to this embodiment of the present invention. The mode selector unit may be implemented in a variety of other possible circuit designs. Furthermore, the present invention is not restricted to memory devices with a configuration of ×4 and ×8. Configuration types of ×16 and ×32 are possible, as well, wherein memory devices can be provided wherein switching may take place between configurations of ×8 and ×16, and ×16 and ×32, respectively. Instead of an electrical fuse element 14, other types of storage units may be utilized which are capable of permanently storing the mode data which indicates the respective configuration type.
The switching devices herein realized as multiplexers 7 and controllable drivers 8 may be replaced by other switching device which is capable of depending on the control signal CS to connect a first number of internal data lines to the respective first number of contact pads 4 or to connect a second number of the internal data lines to the respective second number of contact pads 4. The set of the first number of internal data lines may be a portion of the set of the second number of internal data lines, and the set of the first number of contact pads 4 may be a portion of the set of the second number of contact pads 4.
While the foregoing is directed to embodiments of the present invention, other and further embodiments of the invention may be devised without departing from the basic scope thereof, and the scope thereof is determined by the claims that follow.
