Memory devices having charge trap layers

Abstract

Example embodiments may provide memory devices having a charge trap layer which includes a hole trap and an electron trap. The memory device may generate a relatively large flat band voltage gap according to an applied bias voltage. Accordingly, a stable multilevel cell may be realized.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

Example embodiments will become more apparent by describing them in detail with reference to the attached drawings in which:

FIG. 1 is a cross-sectional view of a conventional non-volatile memory device;

FIGS. 2A and 2B are graphs showing a data programming characteristic and a data erasing characteristic, respectively, of the non-volatile memory device of FIG. 1;

FIG. 3 is a cross-sectional view of a memory device, according to an example embodiment;

FIG. 4 is a cross-sectional view of a memory device, according to another example embodiment;

FIG. 5 is a graph showing a voltage characteristic with respect to a capacitance of the memory device of FIG. 4;

FIG. 6 is a graph showing programming and erasing characteristics as a function of bias voltage application time; and

FIG. 7 is a graph showing the flat band voltage of the memory device of FIG. 4 as a function of time, according to an example embodiment.

Claims

1. A memory device, comprising: a tunnel insulating formed on a substrate;a charge trap layer on the insulating film, including a hole trap and an electron trap;a blocking insulating film on the charge trap layer; anda gate electrode formed on the blocking insulating film.

2. The memory device of claim 1, wherein the hole trap is a first trap layer.

3. The memory device of claim 2, wherein the electron trap is a second trap layer.

4. The memory device of claim 3, wherein the second trap layer is formed on the first trap layer.

5. The memory device of claim 3, wherein the second trap layer is formed of silicon nitride.

6. The memory device of claim 2, wherein the first trap layer is formed of one of a silicon rich oxide and a silicon nano-crystal.

7. The memory device of claim 1, wherein the blocking insulating film is an insulating film having a higher dielectric constant than silicon oxide.

8. The memory device of claim 7, wherein the electron trap is an interface between the blocking insulating film and the first trap layer.

9. The memory device of claim 7, wherein the insulating film is formed of a high k dielectric material.

10. The memory device of claim 9, wherein the high k dielectric material is selected from the group consisting of HfO2, SiNx, Ta2O5, Al2O3, TiO2, and PZT.

11. The memory device of claim 1, further comprising a source region and a drain region in the substrate.

12. The memory device of claim 1, wherein the charge trap layer is a storage node that stores multi-bit data.

13. A method of manufacturing a memory device comprising: forming a tunnel insulating film on a substrate;forming a charge trap layer formed on the insulating film, including a hole trap and an electron trap;forming a blocking insulating film on the charge trap layer; andforming a gate electrode on the blocking insulating film.

14. The method of claim 13, wherein the charge trap layer is a storage node that stores multi-bit data.

15. The method of claim 13, further comprising: forming a source region and a drain region in the substrate.

16. The method of claim 13, wherein the blocking insulating film is an insulating film having a higher dielectric constant than silicon oxide.

17. The method of claim 16, wherein the electron trap is an interface between the blocking insulating film and the first trap layer.

18. The method of claim 16, wherein the insulating film is formed of a high k dielectric material.

19. The method of claim 18, wherein the high k dielectric material is selected from the group consisting of HfO2, SiNx, Ta2O5, Al2O3, TiO2, and PZT.

20. The method of claim 13, wherein, the hole trap is a first trap layer, andthe electron trap is a second trap layer.

21. The method of claim 20, wherein, the first trap layer is formed of one of a silicon rich oxide and a silicon nano-crystal, and the second trap layer is formed of silicon nitride.