This application claims priority to German Patent Application 10 2023 120 085.2, filed on Jul. 28, 2023, the contents of which are hereby incorporated by reference in their entirety.
Exemplary embodiments generally relate to memory readout circuits.
In a semiconductor memory, a decision as to whether a memory cell stores a 0 or a 1 is typically made on the basis of a read current, which is supplied by the memory cell. For this purpose, the read current is compared with a reference, for example by virtue of the read current discharging a pre-charged capacitance and the voltage at the capacitance being compared with a reference voltage. In this way, the read current is converted into a digital signal that has an edge whose temporal position depends on the intensity of the read current. Here, there is a trade off in the fact that, on the one hand, the temporal position of the edge when the memory cell stores a 0 is to be sufficiently different from the temporal position of the edge when the memory cell stores a 1 in order to enable robust readout and, on the other hand, however, it should be possible to read out the memory as quickly as possible. Memory readout circuits that enable these two requirements to be met are desirable.
One embodiment provides a memory readout circuit, comprising a readout node having a capacitance that is discharged by the memory cell to read out a memory cell by means of a cell current, a level detector that is configured to provide a digital output signal and to switch over the output signal when the potential of the readout node (due to the discharge of the readout node) crosses a switching threshold (depending on the selection of the level and the polarity downward or upward, that is to say the switching threshold is overshot or undershot), and a control circuit that is configured to set the switching threshold and/or the switching speed of the level detector depending on the cell current.
The figures do not reflect the actual proportions but are intended to illustrate the principles of the various exemplary embodiments. Various exemplary embodiments are described in detail below with reference to the following figures.
The following detailed description relates to the attached figures, which show details and exemplary embodiments. These exemplary embodiments are described in such great detail that a person skilled in the art is able to carry out the invention. Other embodiments are also possible and the exemplary embodiments may be modified in structural, logic and electrical terms without departing from the subject matter of the invention. The various exemplary embodiments are not necessarily mutually exclusive; rather, various embodiments may be combined with one another to produce new embodiments. Within the scope of this description, the terms “linked”, “connected” and “coupled” are used to describe both a direct and an indirect link, a direct or indirect connection, and direct or indirect coupling.
The memory 100 contains a memory array with a plurality of memory cells 102, wherein each memory cell 102 is connected to a respective word line 101 and a respective bit line 103.
Data can be stored in the memory cells 102 and read out from them again. Memory cells 102 of this kind can be realized on the basis of semiconductors in various technologies, for example flash, RRAM (resistive random access memory) or MRAM (magnetic RAM) technologies. All of these memory technologies have the common feature that, when reading out a memory cell 102, typically a read current (or readout current) is generated or measured, which read current flows in the bit line 103 to which the memory cell 102 that is to be read out is connected (in response to the fact that a certain voltage is applied to the memory cell 101). The word line 101 is used to address the memory cells 102 (in the illustration of
In this case, there are at least two states of the read current; a lower current can represent a logical “0”, a higher current a logical “1”, for example. The aim of a memory readout circuit (traditionally referred to as a “read amplifier”) in this case is to measure the read current and to decide whether a logical “0” state or a logical “1” state exists, that is to say whether a 0 or a 1 was last stored in the memory cell 102.
One way to do this is to first convert the read current into a piece of time information by converting the current I or the flowing charge I*Δt into a voltage ΔU by means of a capacitance C. According to the capacitor formula
The voltage value ΔU increases with the Δt time. An example of this procedure is illustrated in
A readout node 201 of the memory readout circuit 200, which node is connected to a first input of a comparator 202, is charged via a first transistor 203 (in this case a p-channel field-effect transistor, for example a p-MOS (metal-oxide-semiconductor) transistor) to a voltage level Vpre (pre-charge). A second transistor 204 (holding transistor, controlled by a voltage Vhold, in this case an n-channel field-effect transistor, for example an n-MOS transistor) and a multiplexer 205, which switches on the desired bit line (that is to say the bit line to which the memory cell to be read out is connected), is used to connect the readout node 201 to a terminal of the memory cell 206 to be read out, in this case represented by a resistor. A third (n-channel field-effect) transistor 207 is used to connect the other terminal of the memory cell to be read out to ground (that is to say the low supply potential).
Thus, at a time tpre, a connection between the readout node 201 to ground is established via the memory cell 206, that is to say the readout phase is started (the control signal for the first transistor 203 is then set from 0 to 1, so that the pre-charging ends); thus, the read current Icell begins to flow and discharges an integration capacitance Cint 208, so that the voltage at the readout node Vsense starts to decrease continuously from Vpre (the integration capacitance 208 can be considered the capacitance of the readout node). As soon as the readout node 201 reaches the voltage level Vref (which is supplied by a reference voltage source 209, which is connected to the second input of the comparator 203), the comparator 202 switches over and the digital output DO of the comparator changes from a logical zero to a logical one. It is assumed that the memory cell is configured so that the read current is higher when it stores a zero (low resistance of the memory cell), and lower when it stores a one (high resistance of the memory cell). This results in a fast discharge curve 301 or a slow discharge curve 302, respectively, for these two cases. Accordingly, the inputs of comparator 203 when the memory cell stores a zero are earlier (at a time t0) such that the comparator 203 switches over as if the memory cell stores a one (at a time t1).
The minimum read access time Taccess is also indicated in graph 300. This is defined by the time t0, which is given by the discharge current Icell,0 when the memory cell stores a zero:
The time tdelay is in this case the delay of the comparator (that is to say the delay between the time at which the voltage at the readout node 201 becomes lower than Vref and the time at which DO jumps to one). This delay greatly depends on the bias current Ibias of the comparator, represented in
The readout window Twindow is also marked in graph 300. The readout window of the (integration-based) readout process is defined by t1−t0 and thus corresponds to the difference between the cell current for a zero Icell,0 and the cell current for a one Icell,1:
The readout process should on the one hand have the lowest possible minimum read access time, so that it can be read out as quickly as possible, but on the other hand have the largest possible readout window in order to be robust against read errors and noise.
With regard to the read access time (see formula (1)), Tpre is given by the memory area (bit line capacity) and technology parameters, and Icell,0 is determined by the respective memory technology.
Thus, the only remaining design parameters to reduce the read access time are the voltage difference Vpre−Vref and Cint (which must be reduced for this) and the delay tdelay.
With regard to the readout window (see formula (2)), Icell,0 and Icell,1 are determined by the respective memory technology.
Thus, the only remaining design parameter to extend the readout window are the voltage difference Vpre−Vref and Cint (which must be reduced for this).
This results in a trade off between the readout time and the readout window: for a fixed comparator delay, it is not possible to shorten the readout time without shortening the readout window as well.
In accordance with the memory readout circuit 200, the memory readout circuit comprises a precharging circuit 401, a bit-line preparation and holding circuit 402, a multiplexer 403, a memory cell 404 (or is connected to this), an integration capacitance 405 and a comparator 406, which are connected to one another in the manner described in
According to various embodiments, in order to both extend the readout window and keep the readout time low, the cell current is used to actively change the reference voltage 407 of the comparator and also the bias current 408 of the comparator. Specifically, in one exemplary embodiment, the reference voltage 407 and the bias current 408 are increased for a high cell current (that is to say a stored zero), so that the comparator switches faster for a stored zero. For a stored one (low cell current), the reference voltage 407 and the bias current 408 are not increased (but may even be decreased). This shortens the readout time and extends the readout window. This is also referred to below as active readout window extension.
In contrast to the time graph 200, the reference voltage for reading out a zero and a one is now not the same, but the reference voltage for reading out a zero Vref,0 and is higher than the reference voltage for reading out a one Vref,1. In addition, the bias current for reading out a zero is higher than for reading out a one, and thus the delay of the comparator for reading out a zero tdelay,0 is less than the delay of the comparator for reading out a one tdelay,1. This reduces the (minimum) readout time and extends the readout window.
The formulae thus take the place of the forms (1) and (2)
The following text describes memory readout circuits in which Vref and Ibias are variable and depend on the cell current as described above, that is to say provision is made of a control circuit that sets Vref and Ibias depending on the cell current. According to various embodiments, Vref and Ibias are used depending on the charging (or discharge) current by the capacitance Icap=Icell (see
The memory readout circuit 600 is an example of a circuit in which the cell current is measured at the integration capacitance (based on the discharge current of the integration capacitance in the readout phase) and, on this basis, the bias current and/or the reference voltage of the comparator (in the case of the circuit 600, both) are set variably.
Like the memory readout circuit 200 from
The fourth transistor 606 together with a fifth (p-channel field-effect) transistor 607 forms a first current mirror, which provides a reference current Iref, and together with a sixth (p-channel field-effect) transistor 609 forms a second current mirror, which supplies the bias current Ibias to the comparator 602. The fourth transistor 606 is therefore used as a current measuring element and controls the currents Ibias and Iref.
The reference voltage Vref is given by the voltage that drops at a resistor 610 through which the reference current Iref flows (to ground).
If the cell current Icell flows through the memory cell after the pre-charge phase, the integration capacitance is discharged with this current Icell via the fourth transistor 606. This measures the cell current and Vref (that is to say as a product of the reference current Iref and the value of the resistor 610) and Ibias are set via the two current mirrors depending on this cell current. Thus, the switching threshold and the switching speed of the comparator 602 (which is used as a level detector) depend on the cell current.
Therefore, as described with reference to
The control circuit that implements this dependency contains, in particular, the two current mirrors and the resistor 610.
Like the memory readout circuit 200 from
The second terminal of the integration capacitance is furthermore connected to the drain of a fourth (p-channel field-effect) transistor 706.
The fourth transistor 706 together with a fifth (p-channel field-effect) transistor 707 forms a second current mirror, which provides a bias current Ibias to the input node 709 of the inverter 702. The fourth transistor 706 is therefore used as a current measuring element and controls the current Ibias.
The second terminal of the integration capacitance 708 is furthermore connected to the drain of a sixth (n-channel field-effect) transistor 710, the source of which is connected to ground (that is to say the low supply potential).
The sixth transistor 710 receives a bias voltage Vbias as the input voltage at its gate, which causes, in the pre-charge phase, that is to say when Icell is equal to zero, the current mirror to still reflect a certain bias current Ib, that is to say, in the pre-charge phase, the bias current Ibias is equal to Ib.
In the pre-charge phase, that is to say PRE is active (which in this example corresponds to a low level of PRE), the pre-charge voltage Vpre is connected to the readout node 701 via the first transistor 703 and the second terminal of the integration capacitance 708 is connected to ground via the third transistor 704, such that, as in the examples above, the integration capacitance 708 is charged.
In addition, when PRE is active (and therefore
In the readout phase (PRE is now high, that is to say
If the voltage at the readout node (after a time that depends on the level of the cell current Icell) has dropped so far that the seventh transistor 712 blocks, the voltage at the input node DOa of the inverter 702 increases and the inverter 702 switches so that the output signal DO of the inverter 702 assumes a high level. In the case of a high cell current, Ibias is higher and, on the one hand, the node DOa is charged faster and, on the other hand, the switching threshold is changed to VthN1+Vov, from which the node DOa begins to increase.
The circuit 700 achieves a situation in which a possible variation of the threshold voltage VthN1 of the seventh transistor 712 is compensated.
In addition, as with circuit 600 in
Since the integration capacitance 708 is connected to VDD during discharge, the reading of noise in the supply voltage is adversely affected. To avoid this, the sources of the fourth transistor and the fifth transistor can also be supplied with the pre-charge voltage Vpre (instead of VDD) (which is stabilized by a preregulation process, for example).
In the above examples of circuits with active readout window extension, the cell current is determined by measuring the discharge current of the readout capacitance. It is also possible that the readout capacitance is divided and only the discharge current is measured at one of the two partial capacitances. An example of this is shown in
In this example, there are two integration capacitances 1001, 1002 and the discharge current of the second integration capacitance 1002 is measured and, based on this, the bias current and the reference voltage for the comparator 1003 are set. Otherwise, the function is the same as for the circuit of
In summary, according to various embodiments, provision is made for a memory readout circuit as illustrated in
The memory readout circuit 1100 contains a readout node 1101 having a capacitance that is discharged by the memory cell 1104 to read out a memory cell 1104 by means of a cell current.
The memory readout circuit 1100 also contains a level detector 1102 that is configured to provide a digital output signal and to switch over the output signal when the potential of the readout node (due to the discharge of the readout node) crosses a switching threshold (depending on the selection of the level and the polarity downward or upward, that is to say the switching threshold is overshot or undershot), and a control circuit that is configured to set the switching threshold and/or the switching speed of the level detector depending on the cell current.
According to various embodiments, for example, the reference voltage (and thus the switching threshold) and the bias current (and thus the switching speed) of a comparator are actively changed in order to extend the readout window and reduce the access time. This is done, for example, by measuring the current flowing through the integration capacitance in the readout phase and, depending on this, setting the reference voltage and the bias current of the comparator (or generally the switching threshold and the switching speed of the level detector).
According to one embodiment, a memory is provided, comprising a plurality of memory cells and at least one memory readout circuit according to one of the embodiments specified herein, wherein the memory cell that is read out is one of the plurality of memory cells.
Various exemplary embodiments are stated below.
Exemplary embodiment 1 is a memory readout circuit as described with reference to
Exemplary embodiment 2 is a memory readout circuit according to exemplary embodiment 1, wherein the control circuit is configured to set the switching speed to be higher, the higher the cell current is.
Exemplary embodiment 3 is a memory readout circuit according to exemplary embodiment 1 or 2, wherein the crossing is an undershooting and the control circuit is configured to set the switching speed to be higher, the higher the cell current is.
Exemplary embodiment 4 is a memory readout circuit according to exemplary embodiment 1 or 2, wherein the crossing is an overshooting and the control circuit is configured to set the switching speed to be lower, the higher the cell current is.
Exemplary embodiment 5 is a memory readout circuit according to any one of exemplary embodiments 1 to 4, wherein the control circuit is configured to set the switching speed of the level detector by setting a bias current of the level detector.
Exemplary embodiment 6 is a memory readout circuit according to any one of exemplary embodiments 1 to 5, wherein the level detector is a comparator.
Exemplary embodiment 7 is a memory readout circuit according to exemplary embodiment 6, wherein the control circuit is configured to set the switching threshold by setting a reference voltage with which the comparator compares the potential of the readout node.
Exemplary embodiment 8 is a memory readout circuit according to any one of exemplary embodiments 1 to 6, wherein the level detector has an inverter whose input node potential is switched depending on the potential of the readout node.
Exemplary embodiment 9 is a memory readout circuit according to any one of exemplary embodiments 1 to 8, wherein the control circuit is configured to measure the discharge current with which the capacitance is discharged, and to set the switching threshold and/or the switching speed depending on the measured discharge current.
Exemplary embodiment 10 is a memory readout circuit according to any one of exemplary embodiments 1 to 9, wherein the control circuit has at least one current mirror, which is configured to mirror the discharge current with which the capacitance is discharged, and wherein the control circuit is configured to supply the mirrored current to the level detector as a bias current and/or to supply the voltage drop of the mirrored current at a resistor to the level detector as the switching threshold.
Exemplary embodiment 11 is a memory, comprising a plurality of memory cells and at least one memory readout circuit according to any one of exemplary embodiments 1 to 10.
Although the invention has been shown and described primarily with reference to specific embodiments, it should be understood by those familiar with the technical field that numerous modifications may be made with regard to configuration and details thereof, without departing from the essence and scope of the invention as defined by the claims hereinafter. The scope of the invention is therefore determined by the appended claims, and the intention is for all modifications to be encompassed which come under the literal meaning or the scope of equivalence of the claims.
Number | Date | Country | Kind |
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10 2023 120 085.2 | Jul 2023 | DE | national |