Patent Application
20230262988
The invention relates to high-density memory structures, and in particular, the present invention relates to high-density, low read-latency memory structures formed by interconnected thin-film storage elements (e.g., 3-dimensional array of thin-film storage transistors), including those organized as NOR-type memory strings (“NOR memory strings”), and fabrication processes thereof.
A NOR-type memory string includes storage transistors that share a common source region and a common drain region, where each storage transistor can be individually addressed and accessed. U.S. Pat. No. 10,121,553 (the '553 Patent), entitled “Capacitive-Coupled Non-Volatile Thin-film Transistor NOR Strings in Three-Dimensional Arrays,” issued on Nov. 6, 2018, discloses storage transistors (or memory transistors) organized as 3-dimensional arrays of NOR memory strings formed above a planar surface of a semiconductor substrate. The '553 Patent is hereby incorporated by reference in its entirety for all purposes. In the '553 Patent, a NOR memory string includes numerous thin-film storage transistors that share a common bit line and a common source line. In particular, the '553 Patent discloses a NOR memory string that includes (i) a common source region and a common drain region both running lengthwise along a horizontal direction and (ii) gate electrodes for the storage transistors each running along a vertical direction. In the present description, the term “vertical” refers to the direction normal to the surface of a semiconductor substrate, and the term “horizontal” refers to any direction that is parallel to the surface of that semiconductor substrate. In a 3-dimensional array, the NOR memory strings are provided on multiple planes (e.g., 8 or 16 planes) above the semiconductor substrate, with the NOR memory strings on each plane arranged in rows. For a charge-trap type storage transistor, data is stored in each storage transistor using a charge storage film as the gate dielectric material. For example, the charge storage film may include a tunneling dielectric layer, a charge trapping layer and a blocking layer, which can be implemented as a multilayer including silicon oxide or oxynitride, silicon-rich nitride, and silicon oxide, arranged in this order and referred to as an ONO layer. An applied electrical field across the charge storage film adds or removes charge from charge traps in the charge trapping layer, thus altering the threshold voltage of the storage transistor to encode a given logical state in the storage transistor.
Advances in electrically polarizable materials (“ferroelectric materials”), especially those that are being used in semiconductor manufacturing processes, suggest new potential applications in ferroelectric memory circuits. For example, the article “Ferroelectricity in Hafnium Oxide: CMOS compatible Ferroelectric Field Effect Transistors,” by T. S. Böscke et al., published in 2011 International Electron Devices Meeting (IEDM), pp. 24.5.1-24.5.4, discloses a ferroelectric field effect transistor (“FeFET”) that uses hafnium oxide as a gate dielectric material. By controlling the polarization direction in a ferroelectric gate dielectric layer, the FeFET may be programmed to have either one of two threshold voltages. Each threshold voltage of the FeFET constitutes a state, for example, a “programmed” state or an “erased” state, that represents a designated logical value. Such an FeFET has application in high-density memory circuits. For example, U.S. Pat. No. 9,281,044, entitled “Apparatuses having a ferroelectric field-effect transistor memory array and related method,” by D. V. Nirmal Ramaswamy et al., filed on May 17, 2013, discloses a 3-dimensional array of FeFETs.
The present disclosure discloses a memory structure including three-dimensional NOR memory strings of junctionless ferroelectric memory transistors and method of fabrication, substantially as shown in and/or described below, for example in connection with at least one of the figures, as set forth more completely in the claims.
In some embodiments, a three-dimensional memory structure formed above a planar surface of a semiconductor substrate includes multiple memory stacks arranged along a first direction, each memory stack being separated from each of its immediately neighboring memory stacks along the first direction by a trench, each memory stack and each trench extending in a second direction, the first and second directions being orthogonal to each other and both being substantially parallel to the planar surface of the semiconductor substrate. Each memory stack includes at least one active layer, the active layer including a first conductive layer and a second conductive layer spaced apart by a first isolation layer. The trenches include trenches of a first type and trenches of a second type, alternately arranged along the first direction.
The memory structure further includes multiple gate electrode structures provided in the trenches of the first type and arranged spaced apart in the second direction, the gate electrode structures extending in a third direction substantially normal to the planar surface of the semiconductor substrate. Each gate electrode structure includes (i) a semiconductor oxide layer formed on the sidewalls of the trenches of the first type and in contact with the first and second conductive layers; (ii) a ferroelectric dielectric layer provided adjacent the semiconductor oxide layer; and (iii) a gate conductor layer formed adjacent the ferroelectric dielectric layer. The memory structure further includes an isolation material provided in the trenches of the second type.
Each active layer in the memory stack forms multiple thin-film ferroelectric memory transistors organized as a NOR memory string. Each memory transistor is formed at the intersection of the active layer and a gate electrode structure. The multiple memory stacks form multiple NOR memory strings in the trenches of the first type.
These and other advantages, aspects and novel features of the present invention, as well as details of an illustrated embodiment thereof, will be more fully understood from the following description and drawings.
Various embodiments of the invention are disclosed in the following detailed description and the accompanying drawings. Although the drawings depict various examples of the invention, the invention is not limited by the depicted examples. It is to be understood that, in the drawings, like reference numerals designate like structural elements. Also, it is understood that the depictions in the figures are not necessarily to scale.
In embodiments of the present invention, a memory structure includes randomly accessible ferroelectric storage transistors organized as horizontal NOR memory strings. The NOR memory strings are formed over a semiconductor substrate in multiple scalable memory stacks of thin-film storage transistors. The three-dimensional memory stacks are manufactured in a process that includes forming operational trenches for vertical local word lines and forming auxiliary trenches to facilitate back-alley metal replacement and channel separation by a backside selective etch process.
In some embodiments, the ferroelectric storage transistors are thin-film ferroelectric field-effect transistors (FeFETs) having a ferroelectric polarization layer as a gate dielectric layer. The ferroelectric polarization layer, also referred to as a “ferroelectric gate dielectric layer,” is formed adjacent a semiconductor oxide layer as a channel region. The ferroelectric storage transistors include source and drain regions—both formed of a metallic conductive material—in electrical contact with the semiconductor oxide channel region. The ferroelectric storage transistors thus formed are each a junctionless transistor without a p/n junction in the channel and in which the threshold voltage is modulated by the polarization of the mobile carriers in the ferroelectric polarization layer. In the memory structure of the present invention, the ferroelectric storage transistors in each NOR memory string are controlled by individual control gate electrodes to allow each storage transistor to be individually addressed and accessed. In some embodiments, the ferroelectric polarization layer is formed of a doped hafnium oxide material and the semiconductor oxide channel region is formed of an amorphous metal oxide semiconductor material.
In the present description, the term “storage transistor” is used interchangeably with “memory transistor” to refer to the memory device formed in the memory structure described herein. In some examples, the memory structure of the present disclosure including NOR memory strings of randomly accessible storage transistors (or memory transistors) can have applications in computing systems as the main memory where the memory locations are directly accessible by the processors of the computer systems, for instance, in a role served in the prior art by conventional random-access memories (RAMs), such as dynamic RAMs (DRAMS) and static RAMs (SRAMs). For example, the memory structure of the present disclosure can be applied in computing systems to function as a random-access memory to support the operations of microprocessors, graphical processors and artificial intelligence processors. In other examples, the memory structure of the present disclosure is also applicable to form a storage system, such as a solid-state drive or replacing a hard drive, for providing long term data storage in computing systems.
In the present description, the term “semiconductor oxide layer” (sometimes also referred to as “oxide semiconductor layer” or “metal oxide semiconductor layer”) as used herein refers to thin film semiconducting materials made from a conductive metal oxide, such as zinc oxide and indium oxide, or any suitable conductive metal oxides with charge-carriers having mobilities that can be modified or modulated using suitable preparation or inclusion of suitable impurities.
In embodiments of the present invention, the memory structure includes memory stacks where each memory stack includes multiple NOR memory strings formed one on top of another in the vertical direction. In some embodiments, the stacks of NOR memory strings are formed by groups of thin films successively deposited over a planar surface of a semiconductor substrate, each group of thin films being referred to as an “active layer” in the present description. The active layers in each stack of NOR memory strings are provided one on top of another and each active layer is separated from the other active layers by an inter-layer isolation layer. Each active layer includes a common drain line and a common source line that are arranged spaced apart in the vertical direction by a channel spacer dielectric layer. Both the common source line and the common drain line extend along a horizontal direction.
The storage transistors in each NOR memory string share the common source line and the common drain line. The channel layer of the storage transistors is formed on the sidewalls of the memory stacks, in contact with the common source line and the common drain line of each NOR memory string. Gate dielectric layers and gate conductor layers of the storage transistors are formed in a vertical direction in narrow operational trenches between the memory stacks to form storage transistors in multiple parallel planes of each stack, a storage transistor being formed at each intersection of a gate conductor layer and the common source line and the common drain line of a memory string. The gate conductor layers are also referred herein as the local word lines (LWL) and the operational trenches are sometimes referred herein as “LWL trenches.” That is, the operational or LWL trenches are trenches in which the local word line gate conductors are formed and in which storage transistors are fabricated. As mentioned above, the term “vertical” refers to the direction normal to the surface of a semiconductor substrate, and the term “horizontal” refers to any direction that is parallel to the surface of that semiconductor substrate.
In the present embodiments, the storage transistors in the NOR memory strings are ferroelectric field effect transistors including a ferroelectric thin film as the gate dielectric layer, also referred to as the ferroelectric polarization layer or ferroelectric gate dielectric layer or ferroelectric dielectric layer. In a ferroelectric field effect transistor (FeFET), the polarization direction in the ferroelectric gate dielectric layer is controlled by an electric field applied between the transistor drain terminal and the transistor gate electrode, where changes in the polarization direction alters the threshold voltage of the FeFET. In some embodiments, the electric field is applied to both the transistor drain and source terminals, relative to the transistor gate electrode. For example, the FeFET may be programmed to have either one of two threshold voltages, where each threshold voltage of the FeFET can be used to encode a given logical state. For example, the two threshold voltages of the FeFET can be used to encode a “programmed” state and an “erased” state, each representing a designated logical value. In one example, the programmed state is associated with a lower threshold voltage and the erased state is associated with a higher threshold voltage. In some embodiments, more than two threshold voltages may be established to represent more than two memory states at each FeFET.
The memory structure of the present invention realizes many advantages over known or existing memory structures and devices.
First, ferroelectric storage transistors manufactured on vertical walls are very compact and can be manufactured in three-dimensional memory stacks at lower temperatures that are compatible with logic back-end-of-line (BEOL) processes. Ferroelectric storage transistors can operate at lower voltages than conventional charge-trapping storage transistors. These characteristics of the ferroelectric storage transistors enable easy integration of a memory array of three-dimensional horizontal NOR (HNOR) memory strings directly above digital and analog integrated circuits that are built at the surface of a semiconductor substrate. Until recently, ferroelectric transistors had limited endurance. Recent advances in ferroelectric memory research has demonstrated erase/write endurance in excess of 1×1011 cycles as well as fast erase and fast program operations, which enable the use of ferroelectric storage transistors in embedded memory applications. For example, Tan et al. demonstrated ferroelectric memory transistors formed on a crystalline silicon channel with endurance exceeding 1010 cycles. (See, for example, Ava Jiang Tan et al., “Ferroelectric HfO2 Memory Transistors with High-K Interfacial Layer and Write Endurance Exceeding 1010 Cycles,” arXiv:2103.08806 [physics.app-ph], submitted Mar. 16, 2021, available at https://arxiv.org/abs/2103.08806.)
In some embodiments, the ferroelectric storage transistors, as described herein, provide high endurance, long data retention, and relatively low voltage operations for both erase and programming operations (e.g., under +/−5.0 volts). By combining the ferroelectric or polarization characteristics with the 3-dimensional organization (e.g., as the thin-film NOR memory strings described herein), the memory structure of ferroelectric storage transistors of the present invention achieves the additional benefits of high-density, low-cost memory arrays with the advantages of high-speed, randomly accessed memory circuits with low read latency.
Second, the three-dimensional memory structure of the present invention includes ferroelectric storage transistors that use semiconductor oxide layer (or a metal oxide semiconductor layer) as the junctionless channel regions, eliminating the need for heavily doped polysilicon layers for source and drain regions, resulting in a reduced thickness of each active layer in a memory stack as compared to storage transistors formed using traditional polysilicon channel regions with heavily doped semiconductor layers as the source and drain regions. In particular, semiconductor oxide channels have the advantage of high mobility for greater switching performance and without concern for electron or hole tunneling, as compared to traditional polysilicon channels. Ferroelectric storage transistors with junctionless semiconductor oxide channels also support shorter channel length than is possible with polysilicon doped channels while providing lower channel leakage and reduced GIDL (Gate Induced Drain Leakage) effect.
More specifically, the length of the junctionless channel of the ferroelectric transistor can be significantly shorter than the length of the polysilicon channel, thereby allowing the ferroelectric memory structure of the present invention to be more scalable in stack height, making it easier to deposit and etch multiple layers of three dimensional ferroelectric memory strings that make up ever taller memory stacks. In particular, a thinner active layer results in a reduced aspect ratio (AR) for etching the deep trenches between the memory stacks. In turn, reduced aspect ratios allow building more memory planes within a given total height of the three-dimensional memory structure.
In some embodiments, a memory structure of one or more memory layers (or memory planes) of ferroelectric storage transistors can be configured to serve as high density embedded memory in logic integrated circuits; the high density is made possible by the fact that the ferroelectric storage transistors are formed along the vertical walls of memory stack, therefore requiring very little physical space in the horizontal X-Y dimension. For example, the three dimensional ferroelectric memory structure of the present invention can be constructed in the form of a “skyscraper,” allows the formation of a high capacity memory circuit embedded within a logic integrated circuit. Embedding the memory structure of the present invention is made possible by virtue of the relatively low temperatures (typically under 500° C.) required to build the ferroelectric memory stacks, therefore minimizing any damage to the transistors making up the logic integrated circuits sharing the same substrate.
Third, the memory structure of the present invention is formed in a fabrication process in which the channel layer is deposited as a continuous layer on the sidewalls of the memory stacks and which is subsequently separated and isolated to each memory string in the stack by a backside selective etch process using access through a set of auxiliary trenches. In the present description, “auxiliary trenches” refer to trenches that are formed between memory stacks and in which no storage transistors are formed. In embodiments of the present invention, the auxiliary trenches are used advantageously to facilitate a backside selective etch that separates or isolates the channel layer to each memory string. In some embodiment, the auxiliary trenches may further be used to facilitate a backside selective etch that separates the ferroelectric dielectric layer, in addition to the channel layer, formed on the sidewalls of the memory stacks. Furthermore, in some embodiments, the auxiliary trenches are also used to facilitate metal replacement for the common source line and the common drain line.
More specifically, in embodiments of the present invention, the channel layer is isolated to each active layer (i.e., at each memory plane) by etching through access openings provided by a sacrificial layer that is formed between active layers and to be replaced in subsequent process steps by an inter-layer isolation layer. The sacrificial layer is removed in intermediate processing steps to provide the access openings to the backside of the channel layer. In one example, the memory stacks are formed by groups of thin films (active layers) separated by an inter-layer sacrificial layer which is to be subsequently replaced by an inter-layer isolation layer. In one example, the inter-layer sacrificial layer can be an undoped amorphous silicon layer or a silicon germanium layer or a carbon layer, and the inter-layer isolation layer replacing the sacrificial layer can be a low-K dielectric layer or can be an air-gap cavity. During intermediate processing steps, the inter-layer sacrificial layer is removed which provides access openings to the channel layer formed on the sidewall of the stacks at the areas between adjacent active layers. The exposed portion of the channel layer (referred herein as the backside of the channel layer) at each stack is etched using the access openings to separate and isolate the channel layer to each active layer, thereby forming the channel regions for the NOR memory strings in multiple planes.
Fourth, in embodiments of the present invention, the memory structure can be constructed using air gaps as insulation in the vertical direction between the active layers forming the NOR memory strings. Air gaps have a dielectric constant approximately 1.0, which is considerably lower than most dielectric materials, thereby effectively reducing the parasitic capacitance in the vertical direction between an adjacent pair of NOR memory strings in a memory stack. Using air gaps as the isolation between active layers improves the isolation between adjacent NOR memory string and enhances the performance of the memory device formed therefrom. In some embodiment, the inter-layer isolation layer between active layers includes an air gap liner layer to passivate the surfaces of the exposed cavities, the remaining unfilled portion of the cavities forming the air gap isolation.
Furthermore, in some embodiments, the memory structure can implement one or two levels of air gap isolation. As described above, inter-layer air gap isolation can be incorporated to provide insulation between active layers in an active stack. In some embodiments, the memory structure includes a second level of air gap isolation where the cavities between active layers are capped and the remaining unfilled portions of the cavities form air gap isolation in the auxiliary trenches. The air gap isolation in the auxiliary trenches provides isolation and reduces parasitic capacitive coupling between active stacks in the memory structure.
Fifth, in some embodiments, each storage transistor in the stacks of NOR memory strings are isolated from other storage transistors in both the horizontal and the vertical directions. In particular, each NOR memory string in a memory stack is isolated from other NOR memory strings in the same stack by the inter-layer isolation layer, which can be an air gap isolation. The storage transistors in each NOR memory string are further separated and isolated from each other along the NOR memory string (in the horizontal direction). For example, the portions of the channel layer between adjacent local word lines formed in the LWL trenches are removed to isolate the storage transistors along the NOR memory strings in the horizontal direction. In this manner, each storage transistor is completely isolated from any other storage transistors in the same NOR memory string or from storage transistors in NOR memory strings formed in other planes in the same memory stack. The storage transistors in each NOR memory string are controlled by individual gate conductors (also referred to as local word lines or LWL) to allow each storage transistor to be individually addressed and accessed. In some cases, the storage transistors are only isolated in the vertical direction by the inter-layer isolation layer and the channel layer between adjacent local word lines may remain in the LWL trenches. Isolation of the storage transistors in a NOR memory string in the horizontal direction is optional and may be omitted in some embodiments.
These and other advantages of the memory structure of the present invention will be described further in the following description. In the present description, to facilitate reference to the figures, a Cartesian coordinate reference frame is used, in which the Z-direction is normal to the planar surface of the semiconductor surface and the X-direction and the Y-directions are orthogonal to the Z-direction and to each other, as indicated in the figures.
Furthermore, the drawings provided herein are idealized representations to illustrate embodiments of the present disclosure and are not meant to be actual views of any particular component, structure, or device. The drawings are not to scale, and the thickness and dimensions of some layers may be exaggerated for clarity. Variations from the shapes of the illustrations are to be expected. For example, a region illustrated as a box shape may typically have rough and/or nonlinear features. Sharp angles that are illustrated may be rounded. Like numerals refer to like components throughout.
In the present embodiment, the active stacks 17 of the memory structure 10 are separated by narrow trenches including operational trenches 18 (also referred to as “LWL trenches”) and auxiliary trenches 19. In particular, the active stacks 17 are separated by alternating operational trenches 18 and auxiliary trenches 19. In the present description, operational trenches 18 are narrow trenches between active stacks 17 in which the local word line structures are provided and storage transistors are formed. Auxiliary trenches 19 are narrow trenches between active stacks 17 where no storage transistors are formed.
Each active layer 16 includes first and second low resistivity conductive layers (e.g., titanium nitride (TiN)-lined tungsten (W)) separated by a channel spacer dielectric layer (e.g., silicon oxide). During intermediate processing steps, the active layer may include sacrificial layers (e.g., silicon nitride) to be subsequently replaced by conductive layers. Subsequent processing steps form the channel layers, the gate dielectric layers, and the gate conductor layers in the operational trenches 18 between the separated active stacks. The gate conductor layers and the gate dielectric layers are formed as columnar structures extending in the Z-direction. In the present description, the gate conductor layers are also referred to as “local word lines” and the gate conductor layer with a gate dielectric layer is collectively referred to a local word line (LWL) structure 13. The first and second conductive layers of each active strip form a drain region (“common bit line”) and a source region (“common source line”), respectively, of the storage transistors. In the present embodiment, the storage transistors are formed along the vertical side of the active stacks 17 facing the operational trenches 18. In particular, a storage transistor 20 is formed at the intersection of an active strip with the channel layer and an LWL structure 13. The local word line structures 13 in each trench 18 are separated from each other by a dielectric-filled shaft.
In embodiments of the present invention, the storage transistors in the memory structure 10 are junctionless ferroelectric storage transistors. Accordingly, each storage transistor 20 includes only conductive layers as the source and drain regions, without any semiconductor layers. The first and second conductive layers are formed using a low resistivity metallic conductive material. In some embodiments, the first and second conductive layers are metal layers, such as a titanium nitride (TiN)-lined tungsten (W) layer, a tungsten nitride (WN)-lined tungsten (W) layer, a molybdenum nitride (MoN) lined molybdenum (Mo) layer, or a liner-less tungsten or molybdenum or cobalt layer, or other metal layers. The channel spacer dielectric layer 23 between the first and second conductive layers may be a low-k dielectric layer, such as silicon oxide (SiO2). The channel layer 26 is a semiconductor oxide layer. In some examples, the channel layer 26 is formed using an amorphous oxide semiconductor material, such as indium gallium zinc oxide (InGaZnO or IGZO), indium zinc oxide (IZO), indium tungsten oxide (IWO), or indium tin oxide (ITO), or other such semiconductor oxide materials. A semiconductor oxide channel region has the advantage of a high mobility for greater switching performance and without concern for electron or hole tunneling. For example, an IGZO film has an electron mobility of 10.0-100.0 cm2/V, depending on the relative compositions of indium, gallium, zinc and oxygen.
To form the ferroelectric storage transistor, the storage transistor 20 includes a ferroelectric gate dielectric layer or ferroelectric polarization layer 27 in contact with the channel layer 26. The ferroelectric polarization layer 27 serves as the storage layer of the storage transistor. In some embodiments, an interfacial layer 25 may be provided between the semiconductor oxide channel layer 26 and the ferroelectric polarization layer 27. The interfacial layer 25 is a thin layer and may be 0.5 nm to 2 nm thick. In some embodiments, the interfacial layer is formed using a material with a high dielectric constant (K) (also referred to as “high-K” material). In some embodiments, the interfacial layer 25 may be a silicon nitride (Si3N4) layer, or a silicon oxynitride layer, or an aluminum oxide (Al2O3) layer. In one example, the interfacial layer, if present, may have a thickness of 1.5 nm when the ferroelectric polarization layer has a thickness of 4-5 nm. The inclusion of the interfacial layer 25 in
In some embodiments, the ferroelectric polarization layer is formed of a doped hafnium oxide material, such as zirconium-doped hafnium oxide (HfZrO or “HZO”). In other embodiments, the hafnium oxide can be doped with silicon (Si), iridium (Ir) or lanthanum (La). In some embodiments, the ferroelectric polarization layer is a material selected from: zirconium-doped hafnium oxide (HZO), silicon-doped hafnium oxide (HSO), aluminum zirconium-doped hafnium oxide (HfZrAlO), aluminum-doped hafnium oxide (HfO2:Al), lanthanum-doped hafnium oxide (HfO2:La), hafnium zirconium oxynitride (HfZrON), hafnium zirconium aluminum oxide (HfZrAlO), and any hafnium oxide that includes zirconium impurities.
The ferroelectric polarization layer contacts the channel layer 26 on one side and the gate conductor layer 28 on the opposite side. In some embodiments, the gate conductor layer 28 includes a conductive liner 28a as an adhesion layer and a low resistivity conductor 28b. In some examples, the conductive liner 28a is a titanium nitride (TiN) layer, a tungsten nitride (WN) layer, or a molybdenum nitride (MoN), and the conductor 28b is formed using tungsten or molybdenum, or other metals. In some cases, the conductive liner 28a is not needed and the gate conductor layer 28 includes only the low resistivity conductor 28b, such as a liner-less tungsten or molybdenum layer. In other examples, the conductor 28b can be heavily doped n-type or p-type polysilicon, which can be used with or without the conductive liner. The gate conductor layer 28, including the conductive liner 28a (if any) and the conductor 28b, together forms the control gate electrode of the storage transistor and functions as the local word line in the memory structure.
As thus constructed, the semiconductor oxide channel layer 26 forms an N-type, unipolarity channel region where the conductive layers 22, 24 forming the drain and source terminals directly contact the channel region. The ferroelectric storage transistor thus formed is a depletion mode device where the transistor is normally on (i.e., conducting) and can be turned off (i.e., non-conducting) by depleting the N-type carriers in the channel region. The threshold voltage of the ferroelectric storage transistor is a function of the thickness (X-direction) of the semiconductor oxide channel layer 26. That is, the threshold voltage of the ferroelectric storage transistor is the amount of voltage necessary to deplete the carriers within the thickness of the semiconductor oxide channel region to shut off the ferroelectric storage transistor.
Each storage transistor 20 is isolated from adjacent storage transistors along an active stack (in the Z-direction) by the inter-layer isolation layer 15. In the present embodiment, the inter-layer isolation layer 15 is an air gap isolation formed by an air gap cavity 15a and an optional air gap liner 15b. The air gap liner 15b is a dielectric layer used to cover or passivate the exposed surface of the air gap cavity 15a. In some embodiments, the air gap liner 15b is a silicon nitride layer or an aluminum oxide (Al2O3) layer. The air gap liner 15b may be 1 nm-3 nm thick. In
Returning to
In embodiments of the present invention, the three-dimensional array of NOR memory strings of ferroelectric storage transistors can be applied to implement a non-volatile memory device or a quasi-volatile memory device. For example, a quasi-volatile memory has an average retention time of greater than 100 ms, such as about 10 minutes or a few hours, whereas a non-volatile memory device may have a minimum data retention time exceeding 5 years. As a quasi-volatile memory, the ferroelectric storage transistor 20 may require refresh from time to time to restore the intended programmed and erased polarization states. For example, the ferroelectric storage transistors 20 in memory structure 10 may be refreshed every few minutes or hours. In particular, the ferroelectric storage transistors in the present disclosure can form a quasi-volatile memory device where the refresh intervals can be on the order of hours, significantly longer than the refresh intervals of DRAMs which require much more frequent refreshes, such as in tens of milli-seconds.
A salient feature of the ferroelectric storage transistor 20 is that the storage transistor can have a very short channel length, which is operative to increase the voltage separation between the different threshold voltages, while the memory structure 10 can be manufactured without requiring costly lithography techniques to realize the short channel length. In particular, the channel length of the ferroelectric storage transistor 20 is determined by the thickness L1 of the channel spacer dielectric layer 23 (
Referring again to
In some embodiments, the CuA provides the data path to and from the memory array and further to a memory controller that may be built on the same semiconductor substrate as the CuA. Alternatively, the memory controller may reside on a separate semiconductor substrate, in which case the CuA and the associated data path are electrically connected to the memory controller using various bonding techniques. In some examples, the memory controller includes control circuits for accessing and operating the storage transistors in the memory array connected thereto, performing other memory control functions, such as data routing and error correction, and providing interface functions with systems interacting with the memory array.
The memory structure 10 of
In embodiments of the present disclosure, the memory structure includes a memory array portion constructed as described above to form the 3-dimensional array of NOR memory strings. To complete the memory device, the memory structure includes staircase portions provided at the ends of the memory strings (in the Y-directions), as shown in
The memory structure 10 of
In the tile 101, a 3-D NOR memory array 110 is formed in a memory array portion 133. An upper interconnect portion 134 is formed on the memory array portion 133. Interconnects 126 and vias 127 are provided in the insulating film 111 in the upper interconnect portion 134 for forming additional electrical connections. In some embodiments, a conductive pad 128 is provided in the upper interconnect portion 134 for connecting to circuit elements external to the semiconductor memory device. For instance, the passivation film 112 is formed on and encapsulates the upper interconnect portion 134 with an opening exposing at least a part of the conductive pad 128.
In the memory array portion 133, the thin-film storage transistors are organized as a three-dimensional array of NOR memory strings in the memory array portion 102. The memory array portion 102 is provided between staircase portions 103a and 103b. Connections through conductive vias to common bit lines and, optionally, common source lines, of the NOR memory strings are provided in the staircase portions 103a and 103b. In some embodiments, the common source lines are precharged and then held at a relatively constant voltage to serve as a virtual voltage reference during programming, erase and read operations, thereby obviating the need for a continuous electrical connection with the support circuitry during such operations. In
In the memory array portion 102, the thin film storage transistors are formed at the intersection of the common drain line and common source line (collectively referenced by numeral 104) and a local word line 105. A gate dielectric layer 106 is formed between the conductive local word line and the channel layer (not shown in
In the above-described embodiments, the supporting circuitry is described as being formed under the memory array portion 133. Such configuration is illustrative only and not intended to be limiting. For example, in other embodiments, both the memory array portion and the supporting circuitry may be directly formed on the semiconductor substrate 100. In such a case, for example, the supporting circuitry may be located at the periphery of the memory array portion. In other embodiments, the supporting circuitry may be formed on another semiconductor substrate. In such a case, for example, the semiconductor substrate in which the memory array portion is formed and the semiconductor substrate in which the supporting circuitry is formed are bonded after formation of the respective memory and circuit elements.
In some embodiments, the memory device interacts with a memory controller to perform memory operations. As described above, the memory controller includes control circuits for accessing and operating the storage transistors in the memory device, and performing memory control functions, and managing interface functions for host access. In some embodiments, a memory module is formed with the memory device formed on one semiconductor die and the memory controller formed on a separate semiconductor die. The memory die and the memory controller die may be integrated using a variety of integration techniques, such as using TSVs, hybrid bonds, exposed contacts, interposers, printed circuit boards and other suitable interconnect techniques, especially techniques for high density interconnects.
In the present embodiment, the memory controller is embedded in the semiconductor substrate of a logic integrated circuit 160. In particular, the logic integrated circuit 160 may have formed thereon digital or analog logic circuits 162, such as a core processor. The memory controller circuit 166 is integrated into the logic integrated circuit 160 and formed in a portion of the semiconductor substrate of the logic integrated circuit 160. The memory device 150 is bonded to and electrically connected to the memory controller circuit 166 using various bonding techniques. In the present illustration, the memory device 150 includes an array of connectors 156 which are bonded to corresponding mating connectors 158 formed on the logic integrated circuit 160. In some embodiments, the connectors 156 and 158 are hybrid integration bonds, such as copper to copper bonds and may have a pitch of less than 2 micron or less than 1 micron.
As thus configured, the memory device 150, through embedded memory controller 166, operates as an embedded memory circuit in logic integrated circuit 160. The memory controller circuit 166 can be connected to the digital or analog circuits 162 on the logic integrated circuit 160 directly through interconnect lines 168 formed in the logic integrated circuit, without going through any interface circuits. Accordingly, the ferroelectric storage transistors in the memory device 150 become available to circuitry of the logic integrated circuit 160 with minimal delays. That is, the storage transistors can be accessed with low latency through the direct connectors 168 between the memory controller circuit 166 and the logic circuits 162. Such a configuration is sometimes referred to as “in memory compute.” In memory compute is particularly desirable in artificial intelligence and machine learning applications that are data intensive, and which require a great deal of memory in close proximity to the CPU and GPU core processors, which can be formed as the logic circuit 162 in the logic integrated circuit 160. In embodiments of the present invention, memory device 150, including arrays of three-dimensional NOR memory strings of ferroelectric storage transistors, can be used to form an embedded memory circuit to realize a low latency, high capacity in memory compute system for data intensive applications.
In some embodiments, the memory device 150 may be built directly on top of the logic integrated circuit 160 on the same semiconductor substrate. For example, the memory device 150 may be built on top of an insulating layer formed on the logic integrated circuit to protect the circuitry already manufactured. For example, the insulating layer may be a silicon oxide layer or a passivation layer, such as a polyimide layer. Electrical connections between the memory device 150 and the memory control circuit or directly to other application-specific logic circuits are provided through vias formed in the insulating layer. In this case, bonding of the memory device through connectors 156 is obviated.
Referring to
Subsequently, a memory structure 50 is formed by successive depositions of (i) a multilayer 51 and (ii) an inter-layer sacrificial layer 70 on the planar surface of the semiconductor substrate 52, or in particular on the insulating layer 54 formed on the substrate 52. The multilayer 51 includes three sublayers: (a) a first sacrificial layer 72, (b) a channel spacer dielectric layer 63, and (c) a second sacrificial layer 74, in this order in the Z-direction.
In some embodiments, the first and second sacrificial layers 72 and 74 are each a silicon nitride layer. The channel spacer dielectric layer 63 is an insulating dielectric material, such as silicon oxide (SiO2). The third sacrificial layer 70 is a sacrificial material selected from carbon, amorphous silicon (aSi), or silicon germanium (SiGe).
In some embodiments, dummy sublayers may be provided as the lowermost and uppermost layers of memory stack 50 where the dummy sublayers are not necessarily part of an active layer. In the embodiment shown in
After the memory structure 50 is formed with the desired number of multilayers 51 with the third sacrificial layers 70 therebetween, a capping layer 76 is formed on the top of the memory structure. The capping layer 76 is used as a masking layer in subsequent processing, such as for use as a self align mask for forming the local word line structures. In some embodiments, the capping layer 76 is a silicon oxide layer or a silicon oxycarbide (SiOC) layer. A mask 78 is applied on the memory structure (on the capping layer 76) to define trenches to be formed in the memory structure. In some embodiments, the mask 78 is an amorphous hard mask, such as an amorphous carbon hard mask. The mask 78 is patterned, for example, using a photo-lithographical patterning step, to define openings 79 where trenches are to be formed in the memory structure. It is instructive to note that the mask 78 is not drawn to scale in
The use of patterned mask 78 in the present embodiment is illustrative only and not intended to be limiting. Other photo-lithographic and patterning processes can be used to define the openings for forming trenches in the memory structure. In an alternate embodiment, a two-mask process can be used where a first mask is patterned to expose openings for forming a set of operational (or LWL) trenches as well as openings for forming a set of auxiliary trenches, alternately arranged in the X-direction across the memory structure and a second mask is patterned to cover the openings for forming the set of auxiliary trenches and exposes only the openings for the set of operational trenches. The fabrication process continues with the openings of the auxiliary trenches covered by the second mask until the auxiliary trenches are to be formed.
Referring to
Referring to
Thereafter, the memory structure 50 is patterned to form the local word line structures. In the present description, local word line structures refer to the columnar structures formed by the ferroelectric dielectric layer and the gate conductor layer. In the present description, the term “gate electrode structure” is used to refer to a local word line structure and the portions of the channel layer intersecting with the local word line structure. Referring to
More specifically, the etching of the channel layer 66 should be performed to limit any unintended sideway etch into the active stacks of multilayers 51 at the face of the vertical sidewalls of the LWL trenches that have become exposed to the etchant when the channel material 66 has been etched away. By removing the channel material in shafts 88, physical separation of the storage transistors to be formed along each memory string in the Y-direction is realized.
Referring to
In the above-described embodiments, the channel layer 66 is removed during the etch process applied to mask openings 86 to form shafts 88. In other embodiments, the etch process may remove only the sacrificial material 82 and the liner layer 81, without removing the channel layer 66.
To form the local word line structures, the sacrificial material 82 and the liner layer 81 are removed by selective etch from the areas between the dielectric filled shafts 98, exposing the channel layer 66 which remains on the sidewalls of the mesas. The fabrication process then proceeds to form the gate dielectric layer of the storage transistors. Referring to
In the present embodiment, the memory structure 50 is used to form ferroelectric storage transistors and the gate dielectric layer 67 is a ferroelectric polarization layer. The ferroelectric polarization layer 67 can be deposited using an atomic layer deposition (ALD) technique and may have a thickness between 2 nm to 8 nm. A thermal anneal is performed to form the ferroelectric phase in the deposited ferroelectric material. In some embodiments, the thermal anneal of the ferroelectric polarization layer 67 is carried out with a conductive capping layer formed thereon. For example, the gate conductor layer 68 may function as the conductive capping layer in some embodiments. In one embodiment, the ferroelectric polarization layer is formed of a doped hafnium oxide material, such as zirconium-doped hafnium oxide (HfZrO or “HZO”). In other embodiments, the hafnium oxide can be doped with silicon (Si), iridium (Ir) or lanthanum (La). In some embodiments, the ferroelectric polarization layer is a material selected from: zirconium-doped hafnium oxide (HZO), silicon-doped hafnium oxide (HSO), aluminum zirconium-doped hafnium oxide (HfZrAlO), aluminum-doped hafnium oxide (HfO2:Al), lanthanum-doped hafnium oxide (HfO2:La), hafnium zirconium oxynitride (HfZrON), hafnium zirconium aluminum oxide (HfZrAlO), and any hafnium oxide that includes zirconium impurities.
In some embodiments, an interfacial layer 65 may be provided between the semiconductor oxide channel layer 66 and the ferroelectric polarization layer 67. In some embodiments, the interfacial layer 65 is formed using a material with a high dielectric constant (K) (“high-K” material). In some embodiments, the interfacial layer 65 may be a silicon nitride (Si3N4) layer, or a silicon oxynitride layer, or an aluminum oxide (Al2O3) layer and may have a thickness of 1-2 nm. Other materials for the interfacial layer 65 may be indium tungsten oxide. In some embodiments, the interfacial layer 65 may be deposited using an atomic layer deposition (ALD) technique and furthermore, in some embodiments, the interfacial layer 65 may be deposited in the same process chamber as the ferroelectric polarization layer 67, without breaking vacuum between the deposition of the two layers. The interfacial layer 65 is optional and may be omitted in other embodiments of the present invention. In one embodiment, the interfacial layer 65 is an aluminum oxide (Al2O3) layer and is annealed to yield an amorphous film with the desired characteristics. In some embodiments, the aluminum oxide (Al2O3) layer can be annealed in oxygen (O2), ozone (O3), nitrous oxide (N2O), forming gas (H2N2), or argon (Ar). In some embodiments an optional interfacial layer (not shown), similar to the interfacial layer 65, may be deposited on the ferroelectric polarization layer 67.
In the present embodiment, the gate conductor layer 68 is a metal layer and can include a conductive liner 68a and a conductive filler material 68b. The conductive liner 68a may be a titanium nitride (TiN) liner or a tungsten nitride (WN) liner. The conductive filler material 68b may be a metal, such as tungsten (W) or molybdenum (Mo), or heavily doped n-type or p-type polysilicon. In embodiments of the present invention, the gate conductor layer 68, as deposited on the ferroelectric polarization layer 67, functions as a capping layer for the ferroelectric polarization layer which has the beneficial effect of providing tensile stress or compressive force onto the ferroelectric polarization layer to aid in the crystallization of the ferroelectric polarization layer and the formation of the desired ferroelectric crystallization phase—the orthorhombic phase—in the ferroelectric film. In some embodiments, the gate conductor layer 68 is formed by a single conductive layer, such as a titanium nitride (TiN) layer or a tungsten nitride (WN) layer. The single conductive layer is deposited in the excavated cavities on the ferroelectric polarization layer 67. The single conductive layer provides tensile stress or compressive force onto the ferroelectric polarization layer to aid in the crystallization of the ferroelectric polarization layer and the formation of the desired orthorhombic ferroelectric crystallization phase.
In some embodiments, the gate conductor layer 68, including the conductive liner 68a and the conductive filler material 68b, is deposited using atomic layer deposition at a relatively low temperature, such as between 300-400° C. In alternate embodiments, after the deposition of the ferroelectric polarization layer 67, at least the conductive liner 68a is deposited at a reduced temperature, such as a temperature below 350° C., to prevent crystallization of the ferroelectric polarization layer. Thereafter, thermal anneal of the ferroelectric polarization layer is performed with at least the conductive liner 68a as the conductive capping layer to realize the desired ferroelectric crystallization phase (the orthorhombic phase) in the ferroelectric film.
The fabrication process has now formed the vertical local word lines in the LWL trenches. Masks used in the local word line process are removed. Referring to
In some examples, the auxiliary trenches 84 may be 60 nm wide. Each of the second set of trenches 84 is cut between an adjacent pair of the LWL trenches (trenches 80) and each of the second set of trenches 84 is cut substantially equidistant between an adjacent pair of the first set of trenches 80. As a result of trenches 80 and 84 being cut in the multilayer structure, memory stacks in the multilayer structure are formed which are referred to as “active stacks” in the present description. In some examples, the active stacks are each approximately 40 nm wide, which is the width of the bit-lines. The narrow strips resulting from the cutting of the multilayers 51 are referred herein as “active strips” and the multilayer 51 is also referred to as an “active layer.”
In embodiments of the present invention, the fabrication process forms the LWL trenches to house the local word line structures for forming storage transistors with the active stacks bordering the LWL trenches. Meanwhile, the fabrication process forms the auxiliary trenches to facilitate metal replacement and channel separation processes. The auxiliary trenches do not include local word line structures and do not form storage transistors with the bordering active stacks. With the auxiliary trenches 84 thus formed, the fabrication process performs metal replacement where the first and second sacrificial layers 72 and 74 are removed and replaced with the respective first and second conductive layers.
Referring to
Then, referring to
Referring to
Following the metal replacement process, the auxiliary trenches 84 will now be used for separating the channel layer 66 between each multilayer 51, in a process referred to as channel separation. Referring to
As shown in
Returning to the embodiment shown in
Referring to
Referring to
In an alternate embodiment, the remaining cavities 93 in the memory structure 50 are not filled. Instead, the auxiliary trenches 84 are used to provide air gap isolation in the memory structure 50. Referring to
Second, a dielectric layer 96 is formed at the top portions of the auxiliary trenches 84, such as by nonconformal deposition of a dielectric layer. In some examples, a dielectric layer, such as a silicon oxide (SiO2) layer, is deposited at the top portions of the auxiliary trenches 84 around the circumference of the trenches. The deposition process continues by growing the dielectric layer until the dielectric layer merges in the middle of the trenches 84, thereby forming a capping layer covering the remaining cavities 93 of trenches 84. The cap oxide layer 97 may be formed above the completed memory structure 50. The dielectric layer 96 creates an air gap isolation in cavities 93 between adjacent active stacks bordering the auxiliary trenches 84. The dielectric layer 96 implements the second level of air-gap isolation by providing isolation between adjacent memory stacks and reducing the parasitic capacitance therebetween. In particular, the first level of air gap isolation has the effect of minimizing the parasitic capacitive coupling between the first conductive layer (the bit line) in one memory plane and the second conductive layer (the source line) in an adjacent memory plane. The second level of air gap isolation has the effect of minimizing the parasitic capacitance (denoted as Cp) between adjacent active stacks. In some embodiments, the dielectric layer 96 and the dielectric layer 94 are formed of the same dielectric material. In other embodiments, the dielectric layer 96 and the dielectric layer 94 can be formed of different dielectric materials. The dielectric layer 96 and cap oxide layer 97 together provide extra mechanical strength and stability to memory array 50c by preventing listing or collapsing of long strings of tall and narrow memory stacks.
In further embodiments, a memory structure can be constructed to include either one of the two levels of air gap isolation. That is, the memory structure can form the first level of air gap isolation using the dielectric capping layer 94 and the remaining cavities 93 in the auxiliary trenches 84 are filled with a low-K dielectric material, such as silicon oxide (SiO2). Alternately, the memory structure can fill the inter-layer cavities 180 with a low-K dielectric material, such as silicon oxide (SiO2) and the remaining cavities 93 is capped by the dielectric capping layer 96 to form the second level of air gap isolation, without the first level of air gap isolation. The materials or types of isolation used for the inter-layer cavities and the auxiliary trench cavities can be selected based on the amount of desired parasitic isolation between the storage transistors within each active stack and between the active stacks.
Referring to
It is instructive to note that
In the above-described embodiments, the memory structures are formed using a semiconductor oxide layer as the channel layer of the storage transistors. In some embodiments, the semiconductor oxide channel layer is formed as a bi-layer channel including a first semiconductor oxide layer formed on the trench sidewalls and in electrical contact with the conductive layers forming the drain and source lines and a second semiconductor oxide layer formed on the first semiconductor oxide layer. The first and second semiconductor oxide layers together form the channel layer to function as the channel region for each storage transistor. The first semiconductor oxide layer functions as a low contact resistance contact layer to the drain and source conductive layers to which it contacts. The second semiconductor oxide layer functions as the main channel layer providing the desired high mobility and high on-current for the channel region of the storage transistors. In some embodiments, the first semiconductor oxide layer is a metal oxide semiconductor material that provides a contact resistance to the conductive layers that is lower than the contact resistance provided by the second semiconductor oxide layer. In one embodiment, the first semiconductor oxide layer is, for example, an indium aluminum zinc oxide (InAlZnO or IAZO) layer of thickness around 1 nm-2 nm, and the second semiconductor oxide layer is an IGZO layer of thickness around 6 nm. In other embodiments, other semiconductor oxide materials that provide a desirably low contact resistance to metal layers can be used as the first semiconductor oxide layer. In particular, a metal oxide semiconductor material that has high immunity to deoxidization of the channel layer by the source/drain conductive layer and suppresses oxidation of the source/drain conductive layers during thermal processing is desired for use as the first semiconductor oxide layer.
In the above-described embodiments, various memory structures including multiple active layers (or memory planes) have been described. Each memory structure includes multiple memory stacks, each memory stack including multiple active layers, to realize a three-dimensional array of NOR memory strings. The memory structures can be used as the basic building block to form a high capacity, high density memory device including multiple three-dimensional arrays of the NOR memory strings. For example, the three-dimensional arrays of NOR memory strings may be arranged as a two-dimensional array of tiles, each tile including a three-dimensional array of NOR memory strings constructed using a memory structure of the several memory structures described above and including staircase portions and other supporting circuitry, including connecting wiring through global word lines at the top or bottom of each of the tiles.
In embodiments of the present disclosure, a memory structure can be formed using a single active layer. That is, a memory structure can include an array of NOR memory strings formed using a single layer of storage transistors in the vertical direction, the storage transistors being junctionless ferroelectric storage transistors having a semiconductor oxide as the channel and a ferroelectric polarization layer as the gate dielectric layer. In that case, no inter-layer isolation layer is needed. Alternately, a single layer of inter-layer isolation may be provided between the semiconductor substrate and the single active layer. With a single layer of storage transistors, no channel separation is necessary. The auxiliary trenches are used to perform metal replacement to form the first and second conductive layers serving as the common drain line and the common source line. In practice, a memory structure of a single memory plane forms a two-dimensional array of NOR memory strings. A memory device can be formed using such a memory structure where the memory device includes a two-dimensional array of tiles, each tile including a two-dimensional array of NOR memory strings formed using a single memory plane of storage transistors and other supporting circuitry. In a single layer formation, no staircase structure is needed or in the alternate, a staircase structure of only a single staircase step may be used to connect to the bit lines of each NOR memory string. Alternatively, a single layer or two layer ferroelectric memory tiles can have their first layer bit lines and their second layer bit lines connected directly to logic circuits in the substrate underneath the bit lines, through buried contacts serving as vias. In some examples, a memory device thus constructed is suitable for use as an embedded memory for providing high memory capacity within less than 10 microns distance of connectors directly above one or more processor cores for low latency data intensive applications. Accordingly, in one example, a memory device including one or two memory planes may be built integrated into the same semiconductor substrate of a logic integrated circuit to function as an embedded memory to the processing circuit of the logic integrated circuit.
In the above-described embodiments, the channel layer 66 is formed after the LWL trenches are made (
First, referring to
The process of forming the memory structure 50d continues in the same manner as described above with reference to
The resulting memory structure at the end of the fabrication process is shown in
Precharge Transistors
In embodiments of the present invention, a memory structure includes three-dimensional array of NOR memory strings of junctionless ferroelectric storage transistors. The storage transistors in each NOR memory string share the common source line and the common drain line (common bit line). The voltage on each shared common source line can be separately applied directly from one or both ends of each source line in the three-dimensional structure. In some embodiments, the shared common source line is electrically floating and the source voltage is applied from the common bit line using precharge transistors so as to obviate the need to provide connector wires to the source lines at the staircase portions of the three-dimensional structure. In one embodiment, the source voltage on a given source line is set to a desired voltage value (such as the ground voltage) through a precharge operation using one or more precharge transistors formed along the memory string and the source line is then left floating after the precharge operation. In particular, the precharge operation set the common bit line to a desired voltage and then the precharge transistor is momentarily turned on to short the common bit line to the common source line to transfer the bit line voltage to the source line. As a result, the common source line is charged from the voltage on the common bit line to a voltage to equal to the bit line voltage. After the precharge operation is complete, the precharge transistor(s) is turned off. The common source line maintains a relatively constant voltage through the parasitic capacitance at the source terminals, such as the parasitic capacitance between the source terminals and the numerous local word line gate terminals of the storage transistors in the NOR memory string.
In embodiments of the present invention, various schemes can be used to provide precharge transistors in the three-dimensional array of NOR memory strings described above.
In a first embodiment, selected ferroelectric storage transistors in a NOR memory string are designated as precharge transistors.
It is instructive to note that in memory structure 200, a pair of memory strings 210 in each memory plane bordering a LWL trench have corresponding storage transistors sharing a local word line structure. Accordingly, each local word line activates two ferroelectric storage transistors in the memory strings bordering the LWL trench in each memory plane. In one example, in response to the local word line 68-1 being selected, ferroelectric storage transistors 220-1 and 220-2 associated with respective memory strings 210-1 and 210-2 are activated. The common bit lines 62-1 and 62-2 are in turn selected to provide access and the appropriate voltages are provided to the activated ferroelectric storage transistors 220-1 and 220-2. In another example, in response to the local word line 68-2 being selected, ferroelectric storage transistors 220-3 and 220-4 associated with respective memory strings 210-3 and 210-4 are activated. The common bit lines 62-3 and 62-4 are in turn selected to provide access and appropriate voltages are provided to the activated ferroelectric storage transistors 220-3 and 220-4. In some embodiments, when storage transistor 220-1 is to be erased, storage transistor 220-2, which may be in a programmed state, needs to be protected from being erased as well. As an example of a typical erase operation of ferroelectric storage transistor 220-1, the erase operation may require 3.0 Volts applied to the local word line 68-1, and 0.0 Volts applied to its bit line 62-1. To prevent erasing of ferroelectric storage transistor 220-2 (that shares the same local word line 68-1 and therefore has the same 3.0 Volts on its control gate), its bit line 62-2 must be held at an inhibit voltage Vinhb that is close enough to 3.0V to avoid flipping of the polarization state of ferroelectric storage transistor 220-2. The same applies to all program and program inhibit operations, as well as for inhibiting disturbing the polarization state of ferroelectric storage transistors on different planes above or below the plane being accessed, that are not being addressed yet are still being exposed to the voltage on their shared local word lines.
In the present embodiment, a selected number of storage transistors 220 in each memory string 210 are designated for use as precharge transistors 230. In one example, one storage transistor per two hundred and fifty (250) storage transistors along a memory string will be designated as a precharge transistor 230. In a memory string of two thousands (2000) or more storage transistors, 8-10 storage transistors dispersed through the memory string may be designated as precharge transistors.
In each precharge operation, one or more precharge transistors are activated for setting the common source line voltage. In some embodiments, only a subset of the designated precharge transistors is used in each precharge operation. For example, during the precharge operation, one or more designated precharge transistors in a memory string 210 are activated by the memory controller to perform the precharge operation. In one embodiment, the memory controller selects or rotates randomly the physical addresses of the designated precharge transistors from time to time so that different subset of precharge transistors in the memory string are selected over the course of the memory operation. Randomizing the usage of the precharge transistors in each memory string has the effect of reducing electrical stress that may be experienced by each designated precharge transistor over repetitive precharge operations. In one example, after every X-number of precharge operations or after every given time interval, the memory controller changes the physical address of the precharge transistors to be used so that a different subset of precharge transistors in the memory string is selected for use for the next set of X-number of precharge operations. In the present description, the precharge operation may activate one or more precharge transistors and a “subset” of precharge transistors refers to one or more precharge transistors in the present description.
In an alternate embodiment, the memory controller determines through periodic refresh operations the health conditions of the designated precharge transistors. In the event the memory controller determines through the refresh operation that certain precharge transistors have health conditions indicating the transistors are about to fail, such as when a precharge transistor is exhibiting a high leakage current, the memory controller may retire those precharge transistors and replace them with other designated precharge transistors in the respective memory strings.
In a second embodiment, precharge transistors are provided in each NOR memory string as ferroelectric storage transistors, preferably with increased channel width.
In a third embodiment, non-memory transistors are formed in each memory string to use as precharge transistors.
To form the precharge transistors 270 in the memory structure 260 in
Using the mask defining the precharge transistor openings, the liner layer 81 and the sacrificial material 82 covering the channel layer 66 are removed, such as by one or more wet etch process. A gate dielectric layer 272 is then deposited on the sidewalls of the excavated cavities, on the channel layer 66. In one embodiment, the gate dielectric layer 272 is a silicon oxide (SiO2) layer. In other embodiments, the gate dielectric layer 272 can be a hafnium oxide layer (HfO2), or a sandwich of silicon oxide (SiO2) capped by silicon oxynitride (Si2NO3), or aluminum oxide (Al2O3). Then, a conductive layer is deposited to serve as the gate conductor of the precharge transistors 270. The gate conductor may include successively deposited conductive liner layer 274 and low resistivity conductor 276. In some embodiments, the conductive liner layer 274 is a titanium nitride (TiN) layer and the conductor 276 is a heavily doped polysilicon layer or a tungsten (W) layer. Excess deposited materials may be removed from the top of memory structure by CMP. The precharge transistors 270 thus formed are controlled by the conductor 276 as the control gate electrode. Subsequent to forming the precharge transistors 270, the fabrication process may cover the precharge transistors 270 and exposing the areas associated with the memory array to continue manufacturing the storage transistors. In some embodiments, the gate electrode of the precharge transistors 270 are connected to global word lines formed above the memory array which connect to the control circuits formed in the CuA to allow the control circuits or the memory controller coupled thereto to select and activate the precharge transistors 270 to perform precharge operations.
Enhanced Fringing Field Effect
In the memory structure 10 of
In some embodiments, the fringing electric field is further accentuated by biasing the bit line (BL) and the source line (SL) to the same voltage during erase and program operations. In other words, the bit line (BL) and the source line (SL) of the ferroelectric storage transistor is being used as a single electrode during the erase and program operations. With the bit line and the source line biased as a single electrode, the fringing electric fields from both the bit line 22 and the source line 24 extends into the channel 26 from both ends and the fringing electric field overlaps most of, or the entire length of, the channel 26 when the channel is sufficiently short. By biasing the ferroelectric storage transistor in a single electrode mode to accentuate the fringing electric field, the polarization of the ferroelectric dielectric layer is enhanced which can result in a wider threshold voltage window between the erase and program states.
In one embodiment, when the memory structure implements the floating source architecture, the precharge transistors described above can be used to facilitate the equalization of the voltages of the bit line 22 and the source line 24 during erase or program operations so that the bit line 22 and the source line 24 operates as a joint electrode to maximize the fringing field coverage of ferroelectric dielectric layer 27.
In another embodiment of the present invention, the fringing electric field is enhanced by using a high dielectric constant (high-K) dielectric layer in the channel spacer region adjacent the bit line.
In embodiments of the present invention, the channel spacer dielectric layer 320a includes a first dielectric layer 330 and a second dielectric layer 350. The second dielectric layer 350 is formed between the bit line 22 and the first dielectric layer 330. The second dielectric layer 350 has a dielectric constant greater than the dielectric constant of the first dielectric layer 330 and is referred to as a high dielectric constant (high-K) dielectric layer in the present description. In some examples, a high dielectric constant dielectric layer or high-K dielectric as used in the present description refers to a dielectric layer with a dielectric constant greater than the dielectric constant of a silicon oxide layer. By incorporating the high-K dielectric layer 350 adjacent the bit line 22, the fringing electric field between the bit line electrode 22 and the gate electrode 28 is concentrated in the portion of the channel 26 closest to the bit line 22, which has the effect of enhancing the polarization effect of the ferroelectric polarization layer 27 during program and erase operations.
In some embodiments, the high-K dielectric layer 350 can be formed using silicon nitride (having a dielectric constant of about 6) or hafnium oxide (having a dielectric constant of about 19). Other high-K dielectric materials that can be used include silicon oxynitride (SiON). Meanwhile, the first dielectric layer 330 can be formed using silicon dioxide (having a dielectric constant of about 4). In some embodiments, the first dielectric layer 330 has a thickness L2 and the high-K dielectric layer 350 has a thickness L3 and the ferroelectric storage transistor 300 has an effective channel length of L1=L2+L3. In one example, the thickness L2 is 15 nm and the thickness L3 is 10 nm, and the effective channel length of the storage transistor 300 is 25 nm. The high-K dielectric layer 350 may be provided in the fabrication process by including the high-K dielectric layer in the deposition process forming the multilayer stack, such as described with reference to
The higher dielectric constant of the high-K dielectric layer 350 serves to concentrate the fringing electric field that extend over the channel 26 when polarization voltage is applied between the bit line electrode 22 and the control gate electrode 28. The accentuation of the fringing electric field is particularly effective if the bit line conductive layer 22 is very thin (e.g. 20 nm or less), in which case any contribution to the electric field from the field fringing into channel 26 is reinforcing the polarization effect during erase or program operation.
In the embodiment shown in
In some embodiments, dielectric sub-layers 330a and 330b can be silicon dioxide layers while sub-layer 360 can, for example, be an amorphous silicon layer, or a polysilicon layer, or a silicon germanium layer. Sub-layer 360 may be undoped, or can be doped with boron to form a P-type semiconductor layer, or doped with phosphorous to form an N-type semiconductor layer. Sub-layer 360 overlaps with a channel portion 372 of the channel layer 26, which is an oxide semiconductor material, such as IGZO. A dielectric interfacial layer 374 is provided between the sub-layer 360 and the channel portion 372 to isolate the sub-layer 360 from the channel layer 26. In one embodiment, an ultra-thin dielectric interfacial layer 374 (such as between 0.5 nm and 2 nm) is provided between the channel layer 26 and the sub-layer 360. In one embodiment, the dielectric interfacial layer is one of silicon dioxide, silicon nitride, silicon oxynitride, aluminum oxide or a high dielectric constant material, such as hafnium oxide.
As thus configured, sub-layer 360 is capacitively coupled to both the bit line conductive layer 22 and the source line conductive layer 24, denoted by respective capacitor C1 and capacitor C2 in
In the ferroelectric memory transistor 300c, sub-layers 330a, 360 and 330b together make up the channel length L1 of the transistor. In the embodiment shown in
In memory transistor 300d as thus configured, the channel section 372 of the virtual back-gate is made to cover nearly the entire channel length L1 of the channel layer 26. When selected for erase or program, transistor 300d operates as a virtual capacitor at the intersection area between the vertical (in the Z-direction) gate conductor 28 as one capacitor electrode, and the horizontal (in the Y-direction) virtual back-gate 360, in combination with the bit line 22 and the source line 24 together making up the other capacitor electrode. This virtual capacitor configuration enhances the polarization field across the ferroelectric dielectric layer 27 and improves the polarization uniformity across the entire length of the channel 36, which, in the absence of back-gate 360 would depend primarily on the polarization fringing fields at each of bit line 22 and source line 24. The configuration of transistor 300d also improves the threshold voltage uniformity across the memory die as well across a wafer of memory die. This is because the polarization area 372 is essentially shielded from both sides by the closely adjacent polarization areas under bit line 22 and source line 22.
In the ferroelectric memory transistors 300c and 300d of
In some embodiments the voltage on the back-gate 360 is hard-wire connected to external voltage sources by conductive connectors accessed through the auxiliary trenches (not shown in
Referring first to
In embodiments of the present invention, the channel spacer dielectric layer 320e includes a first dielectric layer 330 and a second dielectric layer 356. The second dielectric layer 356, also referred to as a sidewall high-K dielectric layer, is formed between the bit line 22 and the source line 24 and adjacent to and in physical and electrical contact with the channel layer 26. The second dielectric layer 356, as a high-K dielectric layer, has a dielectric constant greater than the dielectric constant of the first dielectric layer 330. In some examples, a high dielectric constant dielectric layer or high-K dielectric layer as used in the present description refers to a dielectric layer with a dielectric constant greater than the dielectric constant of a silicon oxide layer. In some embodiments, the second dielectric layer has a thickness in the X-direction that is between 3-10% of the thickness of the first dielectric layer. By incorporating the high-K dielectric layer 356 on the sidewall of the channel layer 26 between the bit line 22 and the source line 24, the fringing electric field from the bit line electrode 22 and the source line electrode 24 are concentrated in the portion of the channel 26 in the channel spacer region, which has the effect of functioning as a back-gate to enhance the polarization effect of the ferroelectric polarization layer 27 during program and erase operations.
In some embodiments, the high-K dielectric layer 356 can be formed using silicon nitride or hafnium oxide (HfO2) or silicon oxynitride (SiON). Meanwhile, the first dielectric layer 330 can be formed using silicon dioxide. In some embodiments, the first dielectric layer 330 and the sidewall high-K dielectric layer 356 has a thickness in the Z-direction of 20-25 nm, which also establishes the effective channel length of the ferroelectric storage transistors 300e.
In some embodiments, the sidewall high-K dielectric layer 356 can be provided in the fabrication process by forming a recess in the channel spacer insulating layer and etching a conformally deposited high-K dielectric layer. In some examples, after the deposition process of the multilayer stack (e.g.
In some embodiments, the ferroelectric memory transistors 300c and 300d can be formed using the fabrication process described above with reference to
More specifically, the base metal layer 410 can be introduced as an additional sacrificial layer 71 during the deposition of the thin films forming the multilayer 51 and the inter-layer sacrificial layer 70, as shown and described in
In the present embodiment, the memory structure 400 further includes metal bracing provided by the metal pillars of the gate conductors 68 in the Z-direction. During the fabrication of forming the gate conductor layer, such as during the step shown in
In the present description, layer dimensions and thicknesses or materials used to form the three-dimensional NOR memory strings of ferroelectric storage transistors are provided as illustrative examples only and are not intended to be limiting. In other embodiments, other dimension and thickness values or other materials may be used to form the memory structure of the present invention.
The memory structures disclosed herein are illustrated above by arranging junctionless ferroelectric storage transistors in three-dimensional horizontal NOR memory strings. In other embodiments, the memory structures may also be formed by arranging the ferroelectric storage transistors in three-dimensional vertical NOR memory strings, by applying substantially the same principles and methods disclosed herein. Vertical NOR memory strings are described in copending and commonly assigned U.S. patent application Ser. No. 17/559,101, entitled “Vertical NOR Thin-film Transistor Strings and Fabrication Thereof,” filed on Dec. 22, 2021. In some embodiments, the storage transistors of the memory string are arranged along a direction substantially normal to the planar surface of the semiconductor substrate to form vertical NOR memory strings of junctionless ferroelectric storage transistors.
First, referring to
In the present example, the memory structure 50e further includes a topmost inter-layer sacrificial layer 70 and a dummy dielectric layer 610 formed on the topmost inter-layer sacrificial layer 70. The topmost inter-layer sacrificial layer 70 will be subsequently replaced by the inter-layer isolation layer, such as an air gap isolation. The dummy dielectric layer 610 functions as a capping layer for the topmost inter-layer sacrificial layer 70 during the replacement process. In particular, during subsequent processing steps, the topmost inter-layer sacrificial layer is removed to provide access openings to the backside of the channel layer 66. The channel layer 66 is selectively etched through the access openings. Accordingly, the channel layer 66 is isolated to each layer of storage transistors. The dummy dielectric layer 610 is used to provide isolation of the channel layer 66 from the global word line contacts to be formed, as will be explained in more details below.
Thereafter, the memory structure 50e is patterned to form the local word line structures. Referring to
In the present embodiment, after removal of the sacrificial material 82 and the liner layer 81, the exposed channel material 66 is only partially etched in a controlled etch to not etch all the way through the full thickness of the channel layer 66, leaving a much thinner remaining channel material along the exposed sidewalls in shafts 88, as indicated by the dotted circles 99 in
Referring to
To form the local word line structures, the sacrificial material 82 and the liner layer 81 are removed by selective etch from the areas between the dielectric filled shafts 98, exposing the channel layer 66 which remains on the sidewalls of the mesas. The fabrication process then proceeds to form the gate dielectric layer of the storage transistors. Referring to
Then, a gate conductor layer 68 is deposited into the remaining volume of the excavated cavities. For instance, the gate conductor layer 68 may be deposited on the gate dielectric layer 67. After the deposition steps, excess material may be removed from the top of memory structure 50e using, for example, chemical-mechanical polishing (CMP). The resulting memory structure 50e is shown in
In the present embodiment, the gate conductor 68 is formed using a two-step deposition process to deposit two different types of conductive materials. For instance, the gate conductor 68 may be formed with a first deposition step forming a metal cap layer 68a, such as a titanium nitride (TiN) layer or a tungsten nitride (WN) liner, on the ferroelectric polarization layer 67. The deposition of the metal cap layer 68a does not completely filling the trench. The process is followed by a second deposition step of a metal filler layer 68b, such as a tungsten layer, on the metal cap layer to fill the remaining space in each LWL trench. The metal filler layer 68b may be other metal or conductive materials, such as molybdenum (Mo), or heavily doped n-type or p-type polysilicon.
In performing the depositions of layers 65, 67, 68, it is preferable for these depositions to be performed as much as possible without breaking vacuum, or at least minimizing the time between depositions that may cause unwanted surface oxidation of the exposed surfaces. Similarly, it is important that the deposition temperatures, the ambient chemicals existing during depositions, and pre-deposition and post-depositions anneal conditions be optimized for maximum orthorhombic crystallization of the ferroelectric gate dielectric layer.
The process of forming the memory structure 50e continues in the same manner as described above with reference to
Following the metal replacement process, the auxiliary trenches 84 will now be used for separating the channel layer 66 between each active layer 51, in a process referred to as channel separation. Referring to
Referring to
Referring to
In some embodiments, the remaining cavities 93 in the memory structure 50e may be filled with a low-K dielectric material, such as silicon oxide. In the embodiment shown in
As thus formed, the memory structure 50e includes storage transistors arranged in NOR memory strings in multiple planes. In particular, the storage transistors have substantially the same structure as the storage transistor 20 as described in
It is instructive to note that the channel layer 66 for the topmost memory strings in the memory structure 50e is separated and isolated by the topmost isolation layer formed under the dummy dielectric layer 610. Vias 612 can be formed to contact the local word lines (gate conductor layer 668) without concern for possible electrical shorts to the channel layer. Each global word line 614 connects to the local word lines through vias 612 to provide the control signal to the gate electrodes of the storage transistors formed in multiple memory planes associated with the respective vertical local word lines.
In this detailed description, process steps described for one embodiment may be used in a different embodiment, even if the process steps are not expressly described in the different embodiment. When reference is made herein to a method including two or more defined steps, the defined steps can be carried out in any order or simultaneously, except where the context dictates or specific instruction otherwise are provided herein. Further, unless the context dictates or express instructions otherwise are provided, the method can also include one or more other steps carried out before any of the defined steps, between two of the defined steps, or after all the defined steps. For example, formation of the auxiliary (“back alley”) trenches can be implemented partially or in whole, either after formation of the operational (“LWL”) trenches or before formation of the operational trenches. Likewise, formation of the precharge transistors can be completed before or after formation of the operational trenches.
In this detailed description, various embodiments or examples of the present invention may be implemented in numerous ways, including as a process; an apparatus; a system; and a composition of matter. A detailed description of one or more embodiments of the invention is provided above along with accompanying figures that illustrate the principles of the invention. The invention is described in connection with such embodiments, but the invention is not limited to any embodiment. Numerous modifications and variations within the scope of the present invention are possible. The scope of the invention is limited only by the claims and the invention encompasses numerous alternatives, modifications, and equivalents. Numerous specific details are set forth in the description in order to provide a thorough understanding of the invention. These details are provided for the purpose of example and the invention may be practiced according to the claims without some or all of these specific details. For the purpose of clarity, technical material that is known in the technical fields related to the invention has not been described in detail so that the invention is not unnecessarily obscured. The present invention is defined by the appended claims.
This application claims priority to U.S. Provisional Patent Application No. 63/309,994, entitled MEMORY STRUCTURE INCLUDING THREE-DIMENSIONAL NOR MEMORY STRINGS OF JUNCTIONLESS FERROELECTRIC STORAGE TRANSDISTORS AND METHOD OF FABRICATION, filed Feb. 14, 2022, and to U.S. Provisional Patent Application No. 63/330,622, entitled MEMORY STRUCTURE INCLUDING THREE-DIMENSIONAL NOR MEMORY STRINGS OF JUNCTIONLESS FERROELECTRIC MEMORY TRANSDISTORS AND METHOD OF FABRICATION, filed Apr. 13, 2022, which applications are incorporated herein by reference in their entireties.
| Number | Date | Country | |
|---|---|---|---|
| 63330622 | Apr 2022 | US | |
| 63309994 | Feb 2022 | US |
