MEMORY SYSTEM AND CONTROLLER

Abstract

A memory system, which is connected to a host device, includes a memory, a host interface which receives a command and an address, which are output from the host device, and a controller which operates in one of a first mode in which the controller converts the address which is received by the host interface and accesses the memory by using the converted address, and a second mode in which the host device directly accesses the memory by using the address which is received by the host interface, the controller controlling switching between the first mode and second mode in accordance with the command.

Description

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING

FIG. 1 is a block diagram showing an example of the structure of a memory card according to a first embodiment of the invention;

FIG. 2 is a plan view showing an example of the external appearance of the memory card according to the first embodiment and an example of arrangement of pins;

FIG. 3 shows an example of pin assignment in the memory card according to the first embodiment;

FIG. 4 is a schematic view showing a relationship in data arrangement between a NAND-type flash memory which is assumed by a host device in a first mode, and a NAND-type flash memory which is actually mounted in the memory card;

FIG. 5 is a functional block diagram showing an example of the functional structures of the host device and memory card according to the first embodiment;

FIG. 6A is a schematic diagram showing an example of the format of a command which is input to the memory card according to the first embodiment;

FIG. 6B is a schematic diagram showing an example of the format of the command which is input to the memory card according to the first embodiment;

FIG. 7A is a schematic view illustrating a block write operation which is assumed by the host side in the first mode;

FIG. 7B is a schematic view illustrating a block write operation in the memory card according to the first embodiment;

FIG. 8 is a schematic diagram showing an example of the block format of the memory card according to the first embodiment;

FIG. 9 is a timing chart showing an example of signals which are output from the host device when the host device executes data write to the memory card according to the first embodiment in the first mode;

FIG. 10 is a timing chart showing an example of signals which are output from the host device when the host device executes data write to the memory card according to the first embodiment;

FIG. 11 is a flowchart illustrating an example of a test operation in the memory card according to the first embodiment;

FIG. 12 is a block diagram showing an example of the structure of a memory card according to a second embodiment of the invention;

FIG. 13 is a flowchart illustrating an example of a test operation in the memory card according to the second embodiment;

FIG. 14 is a block diagram showing an example of the structure of a memory card according to a third embodiment of the invention;

FIG. 15 is a flowchart illustrating an example of a test operation in the memory card according to the third embodiment;

FIG. 16 is a block diagram for describing the memory card in a pass-through mode according to the third embodiment;

FIG. 17 is a block diagram showing an example of the structure of a memory card according to a fourth embodiment of the invention;

FIG. 18 shows an example of a command sequence for transition to a pass-through mode according to the fourth embodiment;

FIG. 19 shows an example of the command sequence for transition to the pass-through mode according to the fourth embodiment;

FIG. 20 shows an example of the command sequence for transition to the pass-through mode according to the fourth embodiment; and

FIG. 21 shows an example of a command sequence for restoration according to the fourth embodiment.

Claims

1. A memory system which is connected, when used, to a host device, comprising: a nonvolatile semiconductor memory;a host interface which receives a command and an address, which are output from the host device; anda controller which operates in one of a first mode in which the controller converts the address which is received by the host interface and accesses the nonvolatile semiconductor memory by using the converted address, and a second mode in which the host device directly accesses the nonvolatile semiconductor memory by using the address which is received by the host interface, the controller controlling switching between the first mode and second mode in accordance with the command.

2. The memory system according to claim 1, wherein the host interface receives a specific command sequence which is output from the host device, and the controller effects the switching between the first mode and the second mode in accordance with the specific command sequence.

3. The memory system according to claim 1, wherein the controller includes an access path setting unit which sets an access path between the host device and the nonvolatile semiconductor memory at a time of power-on.

4. The memory system according to claim 1, wherein the controller processes, in the first mode, a command sequence which is issued by the host device on an assumption of an erase block size that is less than an erase block size of the nonvolatile semiconductor memory, and controls a write operation, a read operation and an erase operation for the nonvolatile semiconductor memory.

5. The memory system according to claim 1, wherein the controller includes a memory interface which is provided between the controller and the nonvolatile semiconductor memory; and a buffer memory which temporarily stores data which is sent from one of the host device and the nonvolatile semiconductor memory.

6. The memory system according to claim 5, wherein the access path setting unit includes a first switch which is connected between the buffer memory and the host interface, and a second switch which is connected between the buffer memory and the memory interface, the first and second switches changing a connection between the host interface and the buffer memory and a connection between the memory interface and the buffer memory in accordance with switch control signals from a processing unit.

7. A controller mounted in a memory system which is connected, when used, to a host device, comprising: a host interface which receives a command and an address, which are output from the host device; anda processing unit which operates in one of a first mode in which the processing unit converts the address which is received by the host interface and accesses a nonvolatile semiconductor memory by using the converted address, and a second mode in which the host device directly accesses the nonvolatile semiconductor memory by using the address which is received by the host interface, the processing unit controlling switching between the first mode and second mode in accordance with the command.

8. The controller according to claim 7, wherein the host interface receives a specific command sequence which is output from the host device, and the processing unit effects the switching between the first mode and the second mode in accordance with the specific command sequence.

9. The controller according to claim 7, further comprising an access path setting unit which sets an access path between the host device and the nonvolatile semiconductor memory at a time of power-on.

10. The controller according to claim 7, wherein processing unit processes, in the first mode, a command sequence which is issued by the host device on an assumption of an erase block size that is less than an erase block size of the nonvolatile semiconductor memory, and controls a write operation, a read operation and an erase operation for the nonvolatile semiconductor memory.

11. A memory system which is connected, when used, to a host device, comprising: a nonvolatile semiconductor memory;a host interface which receives a command and an address, which are output from the host device; anda controller comprising a first processing unit which executes an overall control of the memory system and stops operating at a time of a pass-through mode, and a second processing unit which is capable of interpreting a command for transition to the pass-through mode and a command for restoration from the pass-through mode, and continues to operate at a time of the pass-through mode.

12. The memory system according to claim 11, wherein the controller further comprises an access path setting unit which sets an access path between the host device and the nonvolatile semiconductor memory at a time of power-on.

13. The memory system according to claim 11, wherein the controller further comprises a clock generating unit which is capable of generating a predetermined clock.

14. The memory system according to claim 13, wherein the controller further comprises a clock path setting unit which effects switching to stop a transmission path of the clock to the first processing unit in accordance with a control by the second processing unit.

15. The memory system according to claim 11, further comprising at least one said nonvolatile semiconductor memory.

16. The memory system according to claim 15, wherein the second processing unit interprets the command for transition to the pass-through mode, which includes a selection command for selecting the at least one said nonvolatile semiconductor memory.

17. The memory system according to claim 11, wherein the controller further comprises a memory interface which is provided between the controller and the nonvolatile semiconductor memory; and a buffer memory which temporarily stores data which is sent from one of the host device and the nonvolatile semiconductor memory.

18. The memory system according to claim 17, wherein the access path setting unit includes a first switch which is connected between the buffer memory and the host interface, and a second switch which is connected between the buffer memory and the memory interface, the first and second switches changing a connection between the host interface and the buffer memory and a connection between the memory interface and the buffer memory in accordance with switch control signals from the second processing unit.

19. The memory system according to claim 18, wherein the clock path setting unit includes a third switch which is connected at least between the clock generating unit and the first processing unit, the third switch changing a connection between the clock generating unit and the first processing unit in accordance with a switch control signal from the second processing unit.