This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2023-101715, filed Jun. 21, 2023, the entire contents of which are incorporated herein by reference.
Embodiments described herein relate generally to a memory system.
A memory system including a memory unit in which a memory cell array is included and controller configured to control the memory unit is proposed.
In general, according to one embodiment, a memory system includes: a memory unit including a memory cell array which includes a plurality of memory cells and which is divided into a plurality of memory cell blocks, and a drive circuit which drives the plurality of memory cells; and a controller which controls the memory unit, wherein each of the plurality of memory cells includes a resistance change memory element and a switching element connected in series to the resistance change memory element, and the controller is configured to control the memory unit in such a manner that the number of times of predetermined access to each of the plurality of memory cell blocks increases or decreases according to a distance from the drive circuit to each of the plurality of memory cell blocks.
Hereinafter the embodiments will be described with reference to the accompanying drawings.
The memory system shown in
The memory unit 100 includes one or more submemory units. In the example shown in
It should be noted that in the following description, in some cases, each of the submemory units 110a and 110b is expressed as a submemory unit 110, each of the memory cell arrays 120a and 120b is expressed as a memory cell array 120, and each of the control circuits 130a and 130b is expressed as a control circuit 130.
It should be noted that the X-direction, Y-direction, and Z-direction shown in
As shown in
More specifically, as shown in
It should be noted that although in the example shown in
The magnetoresistance effect element 40 is a magnetic tunnel junction (MTJ) element and is a nonvolatile memory element. The magnetoresistance effect element 40 has a configuration in which a storage layer (first magnetic layer) 41, reference layer (second magnetic layer) 42, and tunnel barrier layer (nonmagnetic layer) 43 are stacked in the Z-direction.
The storage layer 41 is a ferromagnetic layer having the variable magnetization direction and is constituted of, for example, a CoFeB layer containing therein cobalt (Co), iron (Fe), and boron (B). The variable magnetization direction implies that the magnetization direction is changed by a predetermined write current.
The reference layer 42 is a ferromagnetic layer having the fixed magnetization direction. The reference layer 42 has a configuration in which for example, a CoFeB layer containing therein cobalt (Co), iron (Fe), and boron (B), and superlattice layer of cobalt (Co) and platinum (Pt) are stacked. The fixed magnetization direction implies that the magnetization direction is not changed by the predetermined write current.
The tunnel barrier layer 43 is an insulating layer provided between the storage layer 41 and reference layer 42 and is constituted of, for example, a MgO layer containing therein magnesium (Mg) and oxygen (O).
When the magnetization direction of the storage layer 41 is parallel to the magnetization direction of the reference layer 42, the magnetoresistance effect element 40 is in a low-resistance state in which the resistance thereof is relatively low. When the magnetization direction of the storage layer 41 is antiparallel to the magnetization direction of the reference layer 42, the magnetoresistance effect element 40 is in a high-resistance state in which the resistance thereof is relatively high. Accordingly, the magnetoresistance effect element 40 can store therein binary data according to the resistance state thereof in a nonvolatile manner. Further, it is possible to set one of the low-resistance state and high-resistance state to the magnetoresistance effect element 40 according to the direction in which the write current flows.
The magnetoresistance effect element 40 is a spin transfer torque (STT) magnetoresistance effect element and has perpendicular magnetization. That is, the magnetization direction of the storage layer 41 is perpendicular to the film surface thereof, and magnetization direction of the reference layer 42 is perpendicular to the film surface thereof.
It should be noted that although in
The selector 50 is a two-terminal switching element and has a configuration in which a first electrode 51, second electrode 52, and selector material layer (switching material layer) 53 are stacked in the Z-direction. The selector material layer 53 is formed of, for example, a material in which a metallic element (for example, arsenic) is added to an insulating material (for example, silicon oxide).
As shown in
When a voltage is applied between the wiring line 10 and wiring line 20 shown in
The description is returned to the description of
The controller 200 is a controller configured to control the memory unit 100 on the basis of a command from the host 300 and includes a control circuit 210 and memory 220. The control circuit 210 includes a central processing unit (CPU) and the like and memory 220 includes a dynamic random access memory (DRAM) and the like.
Further, the controller 200 includes interfaces (I/Fs) 230a, 230b, and 240. Transmission/reception of information is carried out between the controller 200 and memory unit 100 through the interfaces 230a and 230b, and transmission/reception of information is carried out between the controller 200 and host 300 through the interface 240.
A drive circuit 141 and drive circuit 142 are included in the control circuits 130 (130a and 130b) shown in
In the memory cell array 120, the plurality of memory cells 30 are included and memory cell array 120 is divided into a plurality of memory cell blocks. In the example shown in
As already described, when the voltage applied to the selector 50 reaches the threshold voltage Vth, the selector 50 enters the on-state and a current flows through the magnetoresistance effect element 40 connected in series to the selector 50. That is, a current flows through the memory cell 30 and it becomes possible to carry out write or read to or from the magnetoresistance effect element 40.
When the selector 50 makes a transition from the off-state to the on-state, a spike current flows through the memory cell 30 and spike voltage is applied to the memory cell 30. For this reason, there is a possibility of deterioration of the memory cell 30 ascribable to a breakdown or the like of the tunnel barrier layer 43 or problem of read disturb or the like occurring. As a result, there is a possibility of the characteristics and reliability of the memory cell 30 being deteriorated.
The magnitude of the spike current (spike voltage) is dependent on the parasitic capacitance and parasitic resistance incidental to the memory cell 30. As the primary factors of the parasitic capacitance and parasitic resistance, the wiring lines (wiring line 10 and wiring line 20) connected to the memory cell 30 and global wiring lines (global word lines and global bit lines) in the drive circuits 140 (drive circuit 141 and drive circuit 142) are conceivable.
When the global wiring lines are thick, the influence of the parasitic capacitance and parasitic resistance of the global wiring lines becomes greater than the influence of the parasitic capacitance and parasitic resistance of the wiring line 10 and wiring line 20. For this reason, the spike current (spike voltage) becomes greater in the memory cells 30 closer to the drive circuit 140 than in the memory cells 30 farther away from the drive circuit 140. Conversely, when the global wiring lines are thin, the spike current (spike voltage) becomes greater in the memory cells 30 farther away from the drive circuit 140 than in the memory cells 30 closer to the drive circuit 140.
Thus in this embodiment, the memory unit 100 is controlled in such a manner that the number of times of access to each of the memory cells 30 in which a large spike current (spike voltage) occurs becomes relatively smaller. Thereby, when viewed as a whole, in the memory unit 100, it is possible to uniformize the degrees of deterioration of the memory cells 30 and prolong the lifetime of the entirety of the memory unit 100.
For example, when the spike current (spike voltage) is greater in the memory cells 30 closer to the drive circuit 140 than in the memory cells 30 farther away from the drive circuit 140, control is carried out in such a manner that the number of times of access to each of the memory cells 30 closer to the drive circuit 140 becomes relatively smaller. Conversely, when the spike current (spike voltage) is greater in the memory cells farther away from the drive circuit 140 than in the memory cells 30 closer to the drive circuit 140, control is carried out in such a manner that the number of times of access to each of the memory cells 30 farther away from the drive circuit 140 becomes relatively smaller.
In order to carry out the control described above, in this embodiment, the memory cell array 120 is divided into a plurality of memory cell blocks BLK according to the distances from the drive circuit 140 to the plurality of memory cell blocks BLK (BLK11 to BLK71).
In the example shown in
The total distance (D1+D2) is minimized in the memory cell block BLK11 and is maximized in the memory cell block BLK71. Further, the memory cell blocks BLK21 and BLK22 belong to a group of the same total distance, memory cell blocks BLK31 to BLK33 belong to a group of the same total distance, memory cell blocks BLK41 to BLK44 belong to a group of the same total distance, memory cell blocks BLK51 to BLK53 belong to a group of the same total distance, and memory cell blocks BLK61 and BLK62 belong to a group of the same total distance.
The controller includes a determination unit 250, memory unit 260, and memory unit 270. The determination unit 250 corresponds mainly to the control circuit 210 of
The memory unit 260 stores therein, with respect to each of the plurality of memory cell blocks BLK of each of the one or more memory cell arrays 120, a first value based on the number of times of predetermined access actually made to each of the plurality of memory cell blocks BLK. In the example of
The predetermined access corresponds to at least one of write access (access configured to write data to the memory cell 30) and read access (access configured to read data from the memory cell 30). That is, the number of times of the predetermined access may be the total number of times of the number of times of the write access and number of times of the read access, may be the number of times of only the write access, or may be the number of times of only the read access.
The first value increases when the number of times of the predetermined access increases. For example, the first value may be the value of the number of times itself of the predetermined access or may be the value correlated with the number of times of the predetermined access.
The memory unit 270 stores therein, with respect to each of the plurality of memory cell blocks BLK of each of the one or more memory cell arrays 120, a second value based on the allowable number of times of the predetermined access to each of the plurality of memory cell blocks BLK. In the example of
As can be seen from the description already given above, the degree of deterioration of the memory cell 30 is dependent on the number of times of access to the memory cell 30 and distance from the drive circuit 140. Accordingly, the allowable number of times of access to the memory cell 30 changes according to the distance from the drive circuit 140. For example, the allowable number of times of access corresponds to the upper limit of the number of times of access and access is disabled with respect to a memory cell 30 which has reached the allowable number of times of access.
On the basis of the items described above, the second value is stored in the memory unit 270 in such a manner that the allowable number of times of the predetermined access to each of the plurality of memory cell blocks BLK (BLK11 to BLK71) increases or decreases according to the distance from the drive circuit 140. The second value increases when the allowable number of times of the predetermined access increases. For example, the second value may be the value of the allowable number of times itself of the predetermined access or may be the value correlated with the allowable number of times of the predetermined access. The second value also increases or decreases according to the distance from the drive circuit 140 as in the case of the allowable number of times of the predetermined access. Normally, regarding the memory cell blocks BLK of the same total distance (D1+D2), the second values of these memory cell blocks BLK are identical to each other. That is, regarding the memory cell blocks BLK belonging to the same group, the second values of the memory cell blocks BLK are identical to each other.
The determination unit 250 determines, on the basis of the first value stored in the memory unit 260 and second value stored in the memory unit 270, a memory cell block BLK to which data should be written out of the plurality of memory cell blocks BLK included in one of the one or more memory cell arrays 120. In the example of
As already described above, the memory unit 260 and memory unit 270 correspond mainly to the memory 220 of
Next, the operation of the memory system according to this embodiment will be described below with reference to the flowchart shown in
When a write command is transmitted from the host 300 (S11), the controller 200 carries out the following operation.
First, the controller 200 temporarily selects one memory cell block BLK from among the plurality of memory cell blocks BLK included in the memory cell arrays 120a and 120b and, with respect to the temporarily selected memory cell block BLK, acquires the first value stored in the memory unit 260 and second value stored in the memory unit 270 (S12).
The determination unit 250 determines, on the basis of the first value and second value, whether or not the temporarily selected memory cell block BLK satisfies the predetermined condition (S13). For example, assuming that the first value is the number of times of the predetermined access and second value is the allowable number of times of the predetermined access, the determination unit 250 determines, with respect to the temporarily selected memory cell block BLK, whether or not the first value is less than the second value.
When the predetermined condition is satisfied (when the first value is less than the second value), the temporarily selected memory cell block BLK is selected (determined) as the memory cell block BLK to which data should be written, and write of data to the selected memory cell block BLK is executed (S14).
When the first value is greater than or equal to the second value, a different memory cell block BLK is temporarily selected and steps of S12 and S13 are carried out on the different memory cell block BLK. In this manner, the steps of S12 and S13 are carried out until the predetermined condition is satisfied and write of data to the memory cell block BLK satisfying the predetermined condition is executed (S14).
As described above, in this embodiment, with respect to each of the plurality of memory cell blocks BLK of each of the one or more memory cell arrays 120, the first value based on the number of times of the predetermined access and second value based on the allowable number of times of the predetermined access are stored, and the memory cell block BLK to which data should be written is determined on the basis of the first value and second value.
Accordingly, by setting the second value in advance according to the position of the memory cell block BLK, it is possible, even when the dimensions of the influence of the spike current (spike voltage) occurring at the time of access to the memory cell 30 differ according to the position of the memory cell 30 in the memory cell array 120, to uniformize the degrees of deterioration of the plurality of memory cells 30 included in the memory unit 100 and prolong the lifetime of the entirety of the memory unit 100.
In particular, when the dimensions of the influence of the spike current (spike voltage) increase or decrease according to the distance from the drive circuit 140, by setting the second value in advance with respect to each of the plurality of memory cell blocks BLK in such a manner that the allowable number of times of the predetermined access increases or decreases according to the distance from the drive circuit 140, it is possible to securely uniformize the degrees of deterioration of the plurality of memory cells 30 included in the memory unit 100.
By setting the second value in advance in the manner described above, it is possible for the controller 200 to control the memory unit 100 in such a manner that the number of times of the predetermined access to each of the plurality of memory cell blocks BLK increases or decreases according to the distance from the drive circuit 140 to each of the plurality of memory cell blocks BLK. For example, on the basis of the first value acquired from the memory unit 260 and second value acquired from the memory unit 270, the determination unit 250 selects (determines) a memory cell block BLK in which a difference between the first value and second value is the largest, whereby it is possible to effectively carry out the control described above.
As can be seen from the description given above, in this embodiment, control is not carried out in such a manner that the numbers of times of the predetermined access are uniformized with respect to the plurality of memory cell blocks BLK unlike in the general wear leveling, and control is carried out in such a manner that the number of times of the predetermined access to each of the plurality of memory cell blocks BLK has a gradient according the distance from the drive circuit 140 in consideration of the fact that the spike currents (spike voltages) differ among the plurality of memory cell blocks BLK. By the control described above, it is possible to uniformize the degrees of deterioration of the memory cells 30 with respect to the plurality of memory cell blocks BLK.
Although in the example shown in
The total distance (D1+D2) is minimized in the memory cell block BLK11 and is maximized in the memory cell block BLK81. Further, the memory cell blocks BLK21 to BLK23 belong to a group of the same total distance, memory cell blocks BLK31 to BLK35 belong to a group of the same total distance, memory cell blocks BLK41 to BLK47 belong to a group of the same total distance, memory cell blocks BLK51 to BLK57 belong to a group of the same total distance, memory cell blocks BLK61 to BLK65 belong to a group of the same total distance, and memory cell blocks BLK71 to BLK73 belong to a group of the same total distance.
In this modified example, the memory cell blocks BLK are further segmentalized according to the distances from the drive circuit 140, and hence it is possible to exhibit the effect of the embodiment described above in a more effective manner.
Although in the example shown in
In the example of
In this modified example too, it is possible to obtain the effect identical to the embodiment described above.
Next, a second embodiment will be described. It should be noted that the fundamental items are identical to the first embodiment and descriptions of the items described in the first embodiment are omitted.
The fundamental configuration of the memory system shown in
It should be noted that as in the case of the first embodiment, in the following description, in some cases, each of the submemory units 110a and 110b is expressed as a submemory unit 110, each of the memory cell arrays 120a and 120b is expressed as a memory cell array 120, each of the control circuits 130a and 130b is expressed as a control circuit 130, and each of the temperature detectors 150a and 150b is expressed as a temperature detector 150.
Further, although in the example shown in
The fundamental functional configuration of the controller 200 shown in
The characteristics and reliability (for example, read disturb probability and breakdown percent defective of the tunnel barrier layer) of the memory cell 30 are normally dependent on the temperature (in particular, temperature of the magnetoresistance effect element 40) of the memory cell 30. For example, the read disturb probability is generally aggravated when the temperature of the memory cell 30 becomes higher. Further, the reliability of the memory cell 30 changes according to the temperature dependence of the write current Ic. That is, regarding the characteristics and reliability of the memory cell 30, there is a case where the characteristics and reliability are aggravated when the temperature becomes higher and there is also a case where the characteristics and reliability are aggravated when the temperature becomes lower.
In this embodiment, on the basis of the temperature dependence of the characteristics and reliability of the memory cell 30 and according to the temperature (ambient temperature) around the memory cell array 120 detected by the temperature detector 150, the second value of each of the plurality of memory cell blocks BLK stored in the memory unit 270 is changed.
More specifically, the second value stored in the memory unit 270 is changed according to the temperature (ambient temperature) around the memory cell array 120 in such a manner as to change the rate (increase rate or decrease rate) at which the allowable number of times of the predetermined access increases or decreases according to the distance from the drive circuit 140.
For example, when the characteristics and reliability of the memory cell 30 are aggravated at the time of a high temperature, the second value is changed in such a manner that the rate at which the allowable number of times of the predetermined access increases or decreases according to the distance from the drive circuit 140 becomes greater at the time of a high temperature than at the time of a low temperature. Conversely, when the characteristics and reliability of the memory cell 30 are aggravated at the time of a low temperature, the second value is changed in such a manner that the rate at which the allowable number of times of the predetermined access increases or decreases according to the distance from the drive circuit 140 becomes greater at the time of a low temperature than at the time of a high temperature.
In this embodiment too, the fundamental configuration and fundamental control method are identical to the first embodiment and, in this embodiment too, it is possible to obtain the effect identical to the first embodiment. Further, by carrying out the control described above, the rate at which the number of times of the predetermined access increases or decreases according to the distance from the drive circuit 140 is effectively changed in accordance with the temperature around the memory cell array 120, i.e., in accordance with the temperature of the usage environment, and it is possible to effectively prolong the lifetime of the entirety of the memory unit 100.
It should be noted that although in the first and second embodiments described above, a magnetoresistance effect element is used as the resistance change memory element, other resistance change memory elements may also be used.
While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. Indeed, the novel devices and methods described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the embodiments described herein may be made without departing from the spirit of the inventions. The accompanying claims and their equivalents are intended to cover such forms or modification as would fall within the scope and spirit of the inventions.
Number | Date | Country | Kind |
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2023-101715 | Jun 2023 | JP | national |