Patent Application
20070088993
Memory chips or components are typically tested after fabrication to ensure that the memory components operate properly. A typical memory test includes writing data to the memory component and then reading the data back from the memory component. The data written to the memory component is compared to the data read from the memory component. If the data written to the memory component matches the data read from the memory component, the memory component is a functioning memory component. If the data written to the memory component does not match the data read from the memory component, the memory component is a defective memory component.
Typical memory testers have a limited number of resources available to test memory components, such as drivers, comparators, power supplies, etc. The fewer resources used to test each memory component, the greater the number of memory components that can be tested simultaneously by the memory tester. Some resource limitations of memory testers include the number of driver circuits used to send inputs to the memory component and the number of driver/comparator circuits used to write data to the memory component and judge the output of the memory component.
Typical test methods use at least one group of driver pins and one or more driver/comparators for each memory component. Some memory testers use a group of driver pins to drive two to four components in parallel, but still use separate driver/comparators for each memory component. Typical test systems use separate driver/comparator pins for all memory components, which severely limits the total number of memory components that can be tested simultaneously. Also, a tester driver is limited in the number of memory component inputs it can drive in parallel due to driver output current limitations. Therefore, in typical test systems the number of memory components that can be tested in parallel is limited by the number of driver/comparator pins available and by the drive current capability of the tester driver pins.
One embodiment of the present invention provides a memory testing system. The memory testing system includes a tester interface. The tester interface is configured to couple a tester control driver to a master memory component and a slave memory component, the tester control driver configured for controlling the master memory component and the slave memory component. The tester interface is configured to couple a tester input/output driver to the master memory component and the slave memory component, the tester input/output driver configured for providing first data to write to the master memory component and the slave memory component and for receiving second data read from the master memory component. The slave memory component is configured to receive the second data and compare the second data to third data read from the slave memory component to determine a test result for the slave memory component. The tester input/output driver is configured to compare the first data to the second data to determine a test result for the master memory component.
Embodiments of the invention are better understood with reference to the following drawings. The elements of the drawings are not necessarily to scale relative to each other. Like reference numerals designate corresponding similar parts.
The tester interface includes hardware to greatly reduce the number of tester control drivers and tester input/output drivers used during a memory test. Memory testing system 100a designates one of the parallel memory components 112 as a master memory component and designates the other memory components 112 as slave memory components. The master memory component provides output data to the slave memory components for the slave memory components to judge their own outputs. This method assumes that the memory components 112 have the capability of judging their own output data if provided with input data to which to compare. The slave memory components under test include an internal test mode that if selected enables the memory components to compare their output data to provided input data.
Memory testing system 100a includes a memory tester including tester driver/comparator 102 (i.e., tester input/output driver), tester driver (address, command, clock, etc.) 106 (i.e., tester control driver), and controller 104. Memory testing system 100a also includes a tester interface including master buffer group 108, slave buffer group 110, and the connections between the tester interface and the memory tester. Testing system 100a is configured to test a suitable number “x” of memory components including component zero 112a, component one 112b, and component two 112c through component X 112(x). Memory component zero 112a is designated as the master memory component and memory component one 112b and memory component two 112c through memory component X 112(x) are designated as slave memory components.
Tester driver/comparator 102 is electrically coupled to controller 104 through communication path 132. Controller 104 is electrically coupled to tester driver (address, command, clock, etc.) 106 through communication path 134. Tester driver/comparator 102 includes input/output (I/O) 0-Y pins or pads 122. I/O 0-Y pins 122 are electrically coupled to master buffer group 108 and slave buffer group 110 through communication path 114. Master buffer group 108 is electrically coupled to memory component zero 112a through communication path 118. Slave buffer group 110 is electrically coupled to memory component one 112b through memory component X 112(x) through communication path 116.
Tester driver (address, command, clock, etc.) 106 includes driver group zero output pins or pads 124a, driver group one output pins or pads 124b, and driver group two output pins or pads 124c through driver group X output pins or pads 124(x). Driver group zero output pins 124a are electrically coupled to control inputs of component zero 112a through communication path 120a. Driver group one output pins 124b are electrically coupled to control inputs of memory component one 112b through communication path 120b. Driver group two output pins 124c are electrically coupled to control inputs of memory component two 112c through communication path 120c, and driver group X output pins 124(x) are electrically coupled to control inputs of memory component X 112(x) through communication path 120(x).
Master buffer group 108 includes output buffer zero 126a, output buffer one 126b, and output buffer two 126c through output buffer Y 126(y), where “y” equals the number of I/O 0-Y pins 122. Master buffer group 108 also includes input buffer zero 128a, input buffer one 128b, and input buffer two 128cthrough input buffer Y 128(y). Slave buffer group 110 includes buffer zero 130a, buffer one 130b, and buffer two 130c through buffer Y 130(y). There is one buffer for each I/O pin connection between tester driver/comparator 102 and slave memory components 112b-112(x). There is one output buffer 126a-126(y) and one input buffer 128a-128(y) for each I/O pin connection between tester driver/comparator 102 and master memory component zero 112a.
Controller 104 controls the operation of memory testing system 100a including the timing of data and control signals through tester driver/comparator 102 and tester driver (address, command, clock, etc.) 106. Tester driver/comparator 102 writes test data to memory components 112a-112(x) and reads test data from master memory component zero 112a. Tester driver/comparator 102 compares the test data written to memory components 112a-112(x) to test data read from master memory component zero 112a. Tester driver (address, command, clock, etc.) 106 provides address command and clock signals to memory components 112a-112(x) for writing test data to and reading test data from memory components 112a-112(x). In one embodiment, memory components 112a-112(x) are random access memories (RAMs), such as dynamic random access memories (DRAMs), synchronous dynamic random access memories (SDRAMs), static random access memories (SRAMs), pseudo-static random access memories (PSRAM), or another suitable type of RAM.
In operation, component zero 112a is designated as the master memory component and is configured to operate in the normal operating mode. Memory components 112b-112(x) are designated as slave memory components and are configured to operate in a test operating mode. In the test operating mode, memory components 112b-112(x) internally compare their output data to provided input data to determine a test result.
Controller 104 controls tester driver (address, command, clock, etc.) 106 and tester driver/comparator 102 to write test data to master memory component zero 112a through master buffer group 108 and to slave memory components 112b-112(x) through slave buffer group 110. Master buffer group 108 and slave buffer group 110 increase the current drive capability of tester driver/comparator 102 to allow greatly increased parallelism from one set of tester driver/comparator pins 122 with little timing skew between write test data for memory components 112a-112(x).
After the test data has been written to memory components 112a-112(x), controller 104 controls tester driver/comparator 102 and tester driver (address, command, clock, etc.) 106 to read the data stored in memory components 112a-112 (x). The test data read from master memory component zero 112a is passed through output buffers 126a-126(y) to I/O 0-Y pins 122 of tester driver/comparator 102. The test data read from master memory component zero 112a is also passed to slave memory components 112b-112(x) through output buffers 126a-126(y) and slave buffers 130a-130(y).
Tester driver/comparator 102 compares the test data that was written to master memory component zero 112a with the test data read from master memory component zero 112a to determine a test result. If the test data written to master memory component zero 112a equals the test data read from master memory component zero 112a, master memory component zero 112a passes the test indicating a functional memory component. If the test data written to master memory component zero 112a does not match the data read from master memory component zero 112a, then master memory component zero 112a fails the test indicating a defective memory component.
With slave memory components 112b-112(x) in a test operating mode, each slave memory component 112b-112(x) internally compares its read test data to the test data passed to the slave memory component from master memory component zero 112a. If the test data passed from master memory component 112a matches the read test data of the slave memory component 112b-112(x), then the slave memory component 112b-112(x) passes the test indicating a functional memory component. If the test data passed from master memory component zero 112a does not match the read test data of the slave memory component 112b-112(x), then the slave memory component 112b-112(x) fails the test indicating a defective memory component. In one embodiment, a chip select pin of each slave memory component is toggled to output the test result for each slave memory component to the memory tester.
I/0 (0-Y)1pins 122a of tester driver/comparator 102 are electrically coupled to master buffer group 108a and slave buffer group 110a through communication path 114a. Master buffer group 108a is electrically coupled to master memory component zero1112a1 through communication path 118a. Slave buffer group 110a is electrically coupled to slave memory components 112b1-112(x1) through communication path 116a. Memory components 112a1-112 (x1) are electrically coupled to buffer group 144a through communication path 140a. Buffer group 144a is electrically coupled to driver group zero pins 124a of tester driver (address, command, clock, etc.) 106 through communication path 142a.
I/O (0-Y)2 pins 122b of tester driver/comparator 102 are electrically coupled to master buffer group 108b and slave buffer group 110b through communication path 114b. Master buffer group 108b is electrically coupled to master memory component zero2 112a2 though communication path 118b. Slave buffer group 110b is electrically coupled to slave memory components 112b2-112 (x2) through communication path 116b. Memory components 112a2-112(x2) are electrically coupled to buffer group 144b through communication path 140b. Buffer group 144b is electrically coupled to driver group one pins 124b of tester driver (address, command, clock, etc.) 106 through communication path 142b. Tester driver/comparator 102 is electrically coupled to controller 104 through communication path 132. Controller 104 is electrically coupled to tester/driver (address, command, clock, etc.) 106 through communication path 134.
Memory testing system 100c includes two master memory components including memory component zero1 112a1 and memory component zero2 112a2. Each master memory component 112a1 and 112a1 is associated with a group of slave memory components 112b1-112(x1) and 112b2-112(x2), respectively. Each master memory component and slave memory component group operates similarly to the single master and slave memory component groups of memory testing systems 100a and 100b. In one embodiment, any suitable number of master memory component and slave memory component groups are tested in parallel by memory testing system 100c.
Embodiments of the present invention provide a memory tester configuration including master and slave memory components and buffers for greatly increasing parallelism from one set of tester driver (address, command, clock, etc.) pins and one set of tester driver/comparator pins. Embodiments of the invention enable a memory tester designed to be a bench test system for testing one memory component at a time to test a plurality of memory components in parallel simultaneously. Embodiments of the invention reduce the cost of the test system by increasing the number of memory components that can be tested in parallel.
