Claims
- 1. A switched-emitter merged device structure, comprising:
- a plurality of field-effect control transistor portions each comprising a source region of a first conductivity type near a first surface of a substantially monocrystalline semiconductor material, and a gate connected to control the flow of carriers of said first conductivity type from said source region through a channel region downwardly into said semiconductor material; and
- a plurality of power bipolar transistor portions each comprising an emitter diffusion of said first conductivity type overlying a portion of a single base diffusion of a second conductivity type;
- wherein said emitter diffusion include a first buried layer having multiple separate spaced apart minimum-geometry emitter diffusion portions on the order of a respective control transistor portion, and said single base diffusion a second buried layer which extends between and connects with adjacent emitter diffusion portions of said first buried layer; and
- wherein individual ones of said emitter diffusions of said bipolar transistor portions are aligned to respective corresponding ones of said control transistor portions for providing an increased emitter diffusion length per unit area such that a current density of said plurality of power bipolar transistor portions is maximized.
- 2. The integrated circuit of claim 1, wherein said semiconductor material consists of silicon.
- 3. The integrated circuit of claim 1, wherein said second buried layer has a dopant concentration per unit area which is greater than 5.times.10.sup.15 cm.sup.-2.
- 4. The integrated circuit of claim 1, wherein said second buried layer has a dopant concentration per unit area which is greater than 1.times.10.sup.16 cm.sup.-2.
- 5. The integrated circuit of claim 1, wherein said bipolar transistor has a beta of less than 50.
- 6. The integrated circuit of claim 1, wherein said bipolar transistor has a base width which is greater than 1 micron.
- 7. The integrated circuit of claim 1, wherein said bipolar transistor has an emitter doping concentration, in proximity to said base diffusion, which is less than three times the doping concentration of said base diffusion in proximity to said emitter diffusion.
- 8. The integrated circuit of claim 1, wherein said first conductivity type is N-type.
- 9. A switched-emitter merged device structure, comprising:
- a plurality of field-effect trench transistor portions each comprising a source region of a first conductivity type near a first surface of a substantially monocrystalline semiconductor material, and an insulated gate connected to control the flow of carriers of said first conductivity type from said source region through a second-conductivity-type channel region along the wall of a trench downwardly into said semiconductor material; and
- a plurality of power bipolar transistor potions each comprising an emitter diffusion of said first conductivity type overlying a portion of a single base diffusion of a second conductivity type;
- wherein said emitter diffusions include a first buried layer having multiple separate spaced apart minimum-geometry emitter diffusion portions on the order of a respective trench transistor portion, and said single base diffusion includes a second buried layer which extends between and connects with adjacent emitter diffusion portions of said first buried layer;
- and wherein said emitter diffusions are aligned in a pattern which predominantly corresponds to the pattern of said trenches for providing an increased emitter diffusion length per unit area such that a current density of said plurality of power bipolar transistor portions is maximized.
- 10. The integrated circuit of claim 9, wherein said semiconductor material consists of silicon.
- 11. The integrated circuit of claim 9, wherein said second buried layer has a dopant concentration per unit area which is greater than 5.times.10.sup.15 cm.sup.-2.
- 12. The integrated circuit of claim 9, wherein said second buried layer has a dopant concentration per unit area which is greater than 1.times.10.sup.16 cm.sup.-2.
- 13. The integrated circuit of claim 9, wherein said bipolar transistor has a beta of less than 50.
- 14. The integrated circuit of claim 9, wherein said bipolar transistor has a base width which is greater than 1 micron.
- 15. The integrated circuit of claim 9, wherein said bipolar transistor has an emitter doping concentration, in proximity to said base diffusion, which is less than three times the doping concentration of said base diffusion in proximity to said emitter diffusion.
- 16. The integrated circuit of claim 9, wherein said first conductivity type is N-type.
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is a continuation-in-part application of U.S. application Ser. No. 08/397,710 (Attorney Docket No. 94-C-131) filed of Feb. 28, 1995 and now U.S. Pat. No. 5,591,655, and therethrough claims priority of the earlier case.
US Referenced Citations (3)
Number |
Name |
Date |
Kind |
5304821 |
Hagino |
Apr 1994 |
|
5410170 |
Bulucea et al. |
Apr 1995 |
|
5471075 |
Shekar et al. |
Nov 1995 |
|
Non-Patent Literature Citations (2)
Entry |
Blanchard, "A Power Transistor With an Integrated Thermal Feedback Mechanism, " Massachusetts Institute of Technology (1970). |
Tukune, et al., "Spontaneous Polysilicon and Epitaxial Silicon Deposition,"J. Electrochem Soc., vol. 142, No. 5 (1995). |
Continuation in Parts (1)
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Number |
Date |
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Parent |
397710 |
Feb 1995 |
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