Commonly used method for forming metal lines and vias is known as “damascene.” Generally, this method involves forming an opening in a dielectric layer, which separates the vertically spaced metallization layers. The opening is typically formed using conventional lithographic and etching techniques. After the formation, the opening is filled with copper or copper alloys to form a via or a trench. Excess metal material on the surface of the dielectric layer is then removed by chemical mechanical polish (CMP). The remaining copper or copper alloy forms vias and/or metal lines.
Copper has replaced aluminum because of its lower resistivity. However, copper still suffers from electro migration (EM) and stress migration (SM) reliability issues as geometries continue to shrink and current densities increase.
The present disclosure is best understood from the following detailed description when read with the accompanying figures. It is emphasized that, in accordance with the standard practice in the industry, various features are not drawn to scale and are used for illustration purposes only. In fact, the relative dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
It is understood that the following disclosure provides many different embodiments, or examples, for implementing different features of the disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Referring to
The first dielectric layer 204 comprises any interlevel or intralevel dielectric including inorganic dielectrics or organic dielectrics. The first dielectric layer 204 may be porous or non-porous. Some examples of suitable dielectrics that can be used as the first dielectric layer 204 include, but are not limited to: SiO2, silsesquioxanes, C doped oxides (i.e., organosilicates) that include atoms of Si, C, 0 and H, thermosetting polyarylene ethers, or multilayers thereof. The term “polyarylene” is used in this application to denote aryl moieties or inertly substituted aryl moieties which are linked together by bonds, fused rings, or inert linking groups such as, for example, oxygen, sulfur, sulfone, sulfoxide, carbonyl and the like.
The first dielectric layer 204 typically has a dielectric constant that is about 3.5 or less, which is referred to as a low-k dielectric layer. More preferably, the first dielectric layer 204 has a k value of less than about 2.5, and hence is sometimes referred to as an extra low-k (ELK) dielectric layer. These dielectrics generally have a lower parasitic crosstalk as compared with dielectric materials that have a higher dielectric constant than 4.0. The thickness of the first dielectric layer 204 may vary depending upon the dielectric material used as well as the exact number of dielectrics within the layer. The first dielectric layer 204 has a thickness, for example applied for an interconnect structure, ranging from about 150 nm to about 450 nm. In some embodiments, the first dielectric layer 204 is formed utilizing a deposition process including chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECV)), evaporation, chemical solution deposition, and spin-on coating.
The first recess cavity 206 is then formed within the first dielectric layer 204 by patterning the first dielectric layer 204. In some embodiments, the patterning process includes applying a lithography process (such as applying a photoresist, exposing the applied photoresist to a desired pattern of radiation and development) on the first dielectric layer 204, then applying an etching process (dry etching, wet etching or a combination thereof) to remove a portion of the first dielectric layer 204 to form the first recess cavity 206 within the first dielectric layer 204. In some embodiments, the first recess cavity 206 is a trench for forming a metal line. In some embodiments, the patterned photoresist is removed by a stripping process before forming the metal line.
Referring to
In some embodiments, a barrier layer 208 is formed before forming the conductive layer 210. In some embodiments, the barrier layer 208 is formed on the exposed wall portions of the first dielectric layer 204 and within the first recess cavity 206. In some embodiments, the barrier layer 208 comprises one of Ti, Ta, TaN, TiN, Ru, RuN, RuTa, RuTaN, W, WN and any other material that can serve as a barrier to prevent conductive material from diffusing there through. The thickness of the barrier layer 208 may vary depending on the deposition process used in forming the same as well as the material employed. In some embodiments, the barrier layer 208 has a thickness ranging from about 0.5 nm to about 40 nm. In alternative embodiments, the barrier layer 208 has a thickness ranging from about 0.5 nm to about 20 nm. In some embodiments, the barrier layer 208 is formed by a deposition process including CVD, PECVD, PVD, atomic layer deposition (ALD), sputtering, chemical solution deposition, and plating.
Referring to
A pretreatment may then be performed to treat the surface of conductive layer 210. In the present embodiment, the pretreatment includes a nitrogen-based gas treatment in a production tool, such as one used for plasma enhanced chemical vapor deposition (PECVD). The nitrogen-based gases, for example, include N2, NH3, and the like. In alternative embodiments, the pretreatment is performed in a hydrogen-based gas environment, which contains hydrogen-containing gases, such as H2, NH3, and the like. The pretreatment on the surface of conductive layer 210 has the function of reducing native metal oxide to metal (e.g., native copper oxide to copper) and removing chemical contamination from the surface of conductive layer 210.
Referring to
The first metallic capping layer 212a may function as an adhesion layer providing sufficient adhesion to the underlying conductive layer 210. In some embodiments, the first metallic capping layer 212a comprises Co, Ir or Ru alone, or their alloy materials with at least one of W, B, P, Mo, or Re. That is, one of Co, Ir, and Ru with at least one of W, B, P, Mo, or Re. In the present embodiment, the first metallic capping layer 212a is a Co-containing metallic capping layer, such as CoWP. In some embodiments, the first metallic capping layer 212a has a thickness within a range from about 0.5 nm to about 20 nm. In alternative embodiments, the first metallic capping layer 212a has a thickness ranging from about 0.5 nm to about 10 nm. In some embodiments, the first metallic capping layer 212a is formed utilizing a selective deposition process including for example, a catalytic plating process or an electroless plating process. In alternative embodiments, a non-selective deposition process such as sputtering, ALD, and CVD can be used.
In some embodiments, the second metallic capping layer 212b is selectively formed on the surface of the first metallic capping layer 212a and has a width substantially similar to the width of the first metallic capping layer 212a. In some embodiments, the second metallic capping layer 212b is formed utilizing a selective deposition process including a catalytic plating process or an electroless plating process. In alternative embodiments, a non-selective deposition process such as sputtering, ALD, and CVD is used to from the second metallic capping layer 212b, hence, the second metallic capping layer 212b may have a width different from the width of the first metallic capping layer 212a.
In the present embodiment, the second metallic capping layer 212b is comprised of a different metal than that which is present in the first metallic capping layer 212a. In some embodiments, the second metallic capping layer 212b includes a material with a resistivity lower than the resistivity of the first metallic capping layer 212a to decrease the combined resistance of the first capping layer 212. In alternative embodiments, the second metallic capping layer 212b includes a material with a deposition rate higher than the deposition rate of the first metallic capping layer 212a to increase the throughput of the production. In some embodiments, the second metallic capping layer 212b is comprised of one of W, Ir, Ru, or alloys thereof. In some embodiments, the second metallic capping layer 212b has a thickness within a range from about 0.5 nm to about 50 nm. In alternative embodiments, the second metallic capping layer 212b has a thickness ranging from about 0.5 nm to about 10 nm.
Referring to
In some embodiments, an etch stop layer (ESL) 214 is formed between the first dielectric layer 204 and the second dielectric layer 216. The second recess cavities 218 are formed in the ESL 214 and the second dielectric layer 216 by a pattering and an etching processes as mentioned above. In some embodiments, the ESL 214 includes a material different from the first dielectric layer 204 or the second dielectric layer 216 to provide an etching selectivity during the process for forming the second recess cavities 218. In some embodiments, the ESL 214 includes silicon nitride, silicon carbide, silicon oxynitride, or combinations thereof.
In some embodiments, the second recess cavities 218 include an upper trench portion 218U for forming a conductive line subsequently. The second recess cavities 218 may further include a lower via portion 218L under the upper trench portion 218U for forming a conductive via subsequently. In the present embodiment, the lower via portion 218L exposes at least a portion of the upper surface of first capping layer 212. The conductive line and via formed using dual damascene processes may function as a second interconnect level over the first interconnect level.
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In some embodiments, the conductors 222 are continuously formed over the barrier layer 220 as the manner for forming the conductive layer 210. In some embodiments, the conductors 222 over-fill the recess cavities 218. In some embodiments, the conductors 222 include copper or copper alloys. In some embodiments, the steps for forming the conductors 222 further include depositing a thin seed layer of copper or copper alloy prior forming the copper or copper alloys. In some embodiments, a CMP process is provided to remove the excess barrier layer 220 and the conductors 222 on the surface of the second dielectric layer 216 while leaving the barrier layer 220 and the conductors 222 in the second dielectric layer 216 and/or in the ESL 214. The remaining barrier layer 220 and the conductors 222 in the second dielectric layer 216 may function as a second interconnect level. As illustrated in
Referring to
The first metallic capping layer 224a may function as an adhesion layer providing sufficient adhesion to the underlying conductors 222. In some embodiments, the first metallic capping layer 224a comprises Co, Ir, or Ru alone, or their alloy materials with at least one of W, B, P, Mo, or Re. In some embodiments, the first metallic capping layer 224a comprises a material same as the material of the first metallic capping layer 212a. In the present embodiment, the second metallic capping layer 224b is comprised of a metal different from the metal present in the first metallic capping layer 212a. In some embodiments, the second metallic capping layer 224b includes a material with a resistivity lower than the resistivity of the first metallic capping layer 224a to decrease the combined resistance of the first capping layer 224. In alternative embodiments, the second metallic capping layer 224b includes a material with a deposition rate higher than the deposition rate of the first metallic capping layer 224a to increase the throughput of the production. In some embodiments, the second metallic capping layer 224b is comprised of one of W, Ir, Ru, or alloys thereof. In some embodiments, the first metallic capping layer 224a and the second metallic capping layer 224b are formed utilizing a selective deposition process including for example, a catalytic plating process or an electroless plating process. In alternative embodiments, a non-selective deposition process such as sputtering, ALD, and CVD can be used.
The embodiments of the present invention have several advantageous features. The first metallic capping layer may provide sufficient adhesion to the underlying conductor, therefore, it may result strong mechanical strength between the first metallic capping layer and the underlying conductor. In addition, the second metallic capping layer has a resistivity lower than the first metallic capping layer. Accordingly, the combined resistances of the first and the second metallic capping layers are reduced. Further, the second metallic capping layer may be formed with a deposition rate higher than the first metallic capping layer. Accordingly, the combined deposition time of the first and the second metallic capping layers is reduced, which causes the improvement in throughput.
In one embodiment, an integrated circuit structure includes a substrate, a dielectric layer over the substrate, a conductive wiring in the dielectric layer, a first metallic capping layer over the conductive wiring, and a second metallic capping layer over the first metallic capping layer. The second metallic capping layer has a width substantially the same as a width of the first metallic capping layer.
In another embodiment, an integrated circuit structure includes a semiconductor substrate, a low-k dielectric layer over the semiconductor substrate, an opening extending from a top surface of the low-k dielectric layer into the low-k dielectric layer, a barrier layer lining the opening, a copper-containing conductive line in the opening and on the barrier layer, a first metallic capping layer over the copper-containing conductive line, and a second metallic capping layer over the first metallic capping layer. The second metallic capping layer comprises a material different from a material of the first metallic capping layer.
In still another embodiment, a method includes forming a dielectric layer over a semiconductor substrate, forming a copper line in the dielectric layer, forming a first metallic capping layer over the copper line, and selectively forming a second metallic capping layer on the first metallic capping layer.
Although the present invention and its advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims. Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, and composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the disclosure of the present invention, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed, that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the present invention. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps.
This application claims priority to U.S. Provisional Patent Application No. 61/780,767, filed Mar. 13, 2013, and entitle “Metal Capping Layer for Interconnect Applications,” which application is incorporated herein by reference.
Number | Date | Country | |
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61780767 | Mar 2013 | US |