Patent Application
20060027924
This invention generally relates to multi-layered semiconductor structures and more particularly to a method for preventing stress-induced cracking in multi-level integrated circuit devices.
The escalating requirements for high density and performance associated with ultra large scale integration semiconductor wiring require increasingly sophisticated interconnection technology. As device sizes decrease it has been increasingly difficult to provide interconnection technology that satisfies the requirements of low RC (resistance capacitance) metal interconnect properties, particularly where sub-quarter micron characteristic dimension integrated circuit wiring is formed in multiple stacked levels (dielectric layers).
In the fabrication of semiconductor devices, increased device density requires multiple levels of wiring, making necessary the provision of a multi-layered metal interconnect structures. Such a multi-layered interconnect structure typically includes inter-layer metal interconnects (wiring), also referred to as vias and intra-layer metal interconnects, also referred to as trench lines. The intra-layer metal interconnects including trench lines are also referred to as metallization layers, typically including metal damascene structures formed in one or more dielectric insulating layers. In one manufacturing approach, trench lines are formed overlying and encompassing vias to form dual damascene interconnect structures where both the via and trench line openings are simultaneously filled with metal.
In a typical process for forming multiple layer interconnect structure, for example, a dual damascene process, a dielectric insulating layer, also referred to as an inter-metal dielectric (IMD), is deposited for forming damascene metal interconnects, also referred to as a metallization layer, e.g., M1, M2, M3, etc., depending on the number of preceding metallization layers. In one approach to forming a dual damascene structure a high aspect ratio opening referred to as a via is then etched through the dielectric insulating layer by conventional photolithographic and etching techniques. Another etched opening referred to as a trench line is then formed overlying and encompassing one or more via openings. The via opening and the trench line together makeup the dual damascene structure which is subsequently filled with metal, for example, copper, followed by a planarization process such as a chemical mechanical polish (CMP) to prepare the process surface for formation of another overlying metallization layer in a multi-level semiconductor device.
Signal transport speed is of great concern in the semiconductor processing art for a number of reasons. The signal transport speed of semiconductor circuitry, also referred to as the RC time constant, varies inversely with the resistance and capacitance (RC) of the interconnections. As integrated circuits become more complex and feature sizes decrease, the effect of the RC time constant on signal delay becomes critical. The formation of multi-level integrated circuit devices increasingly requires novel manufacturing approaches to reduce the capacitance of the dielectric layers while maintaining device robustness to withstand processing and operating induced thermal stresses.
For example, one way to reduce capacitance is to reduce the capacitance of the dielectric insulating layers making up the multi-layered IC device. Several approaches have been proposed including the use of low dielectric constant (low-K) materials for forming the metallization and IMD layers. For example, the use of silicon dioxide based porous materials has been one low-K material that has been used with some success. The use of porous low-K materials has a major drawback, however, in that they typically have lowered strength and are more susceptible to stress-induced cracking. For example, in a multi-level IC device manufacturing process each layer is subjected to thermal stresses during and following the manufacturing process. The magnitude of the stresses, for example tensile stresses, produced in each level of the IC device produce a cumulative effect of increasing stress with the formation of each successive overlying level of the IC device. The probability of catastrophic failure (e.g., cracking) of the dielectric insulating layers increases with the formation of each successive metallization layer. The presence of cracking in the dielectric layers is frequently difficult to detect, and when detected results in scrapping of the IC device. Such stress-induced cracking is therefore a limiting factor in the integration of multi-level IC devices, reducing both yields and the reliability of the IC device.
There is therefore a need in the integrated circuit processing art to provide a multi-level metallization layer structure and method for forming the same to reduce the cumulative effect of stress buildup thereby reducing the incidence of cracking failure in multi-level integrated circuit devices to improve both yield and reliability.
It is therefore among the objects of the present invention to provide a multi-level metallization layer structure and method for forming the same to reduce the cumulative effect of stress buildup thereby reducing the incidence of cracking failure in multi-level integrated circuit devices to improve both yield and reliability, in addition to overcoming other shortcomings and deficiencies in the prior art.
To achieve the foregoing and other objects, and in accordance with the purposes of the present invention, as embodied and broadly described herein, the present invention provides a stacked metallization layer integrated circuit structure and method for forming the same for reducing a tensile stress thereby improving a resistance to cracking.
In a first embodiment, the method includes providing a semiconductor process wafer; forming a dielectric insulating layer over the semiconductor process wafer comprising at least one intervening dielectric layer formed in compressive stress at a level adjacent to at least one of a via portion and a trench portion comprising a subsequently formed metal filled dual damascene; and, forming the metal filled damascene.
These and other embodiments, aspects and features of the invention will become better understood from a detailed description of the preferred embodiments of the invention which are described in conjunction with the accompanying drawings.
Although the method of the present invention is explained by exemplary reference the formation of a dual damascene structure according to a via-first method of formation in a multi-level semiconductor device it will be appreciated that the method of the present invention is equally applicable to other methods of dual or single damascene structure formation including for example stacked vias and damascene structures such as bonding pads. While the method of the present invention is particularly advantageously implemented with respect to copper filled dual damascene structures, it will be appreciated that the method may be adapted for use with other metal fillings, for example including tungsten, aluminum, and copper and alloys thereof. Further, the term ‘copper’ will be understood to include copper and alloys thereof.
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The first dielectric insulating layer portion 12A, for example is formed by a PECVD process including organo-silane precursors such as methylsilanes, for example, tetramethylsilane and trimethylsilane. In addition, organo-siloxane precursors such as cyclo-tetra-siloxanes may be used to form the first dielectric insulating layer portion 12A.
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The thin dielectric layer portion 14A is preferably formed of one or more layers of silicon nitride (e.g., SiN), silicon oxynitride (e.g., SiON), silicon carbide (e.g., SiC), silicon oxycarbide (e.g., SiOC or SiCO), and silicon carbide nitride (e.g., SiCN). It will be appreciated that stoichiometry of the respective dielectric layers may be varied according to known CVD processing variables, including altering relative ratios of reactants to achieve a desired compressive stress of the film.
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In a preferred embodiment of the invention, a metal capping layer e.g., 20A is preferably selectively deposited to form a protective layer over the upper portion of the copper filled dual damascene 16A. A recessed area in the upper portion of the copper filled dual damascene e.g., 16A may first be formed by CMP overpolishing or formed by chemically or thermally oxidizing upper portions of the planarized copper portion followed by wet etching away the formed copper oxide to from a recessed area having an exposed copper portion at the upper portion of the dual damascene, for example having a depth from about 100 Angstroms to about 300 Angstroms. Preferably, the metal capping layer e.g., 20A is formed over the exposed copper portion by electroless deposition of a nickel, tungsten or cobalt alloy, such as CoWP, and CoWB, more preferably COWB. For example, an electroless plating solution including a reducing agent is used to plate out metallic constituents in the plating solution selectively onto the upper exposed copper portion of the dual damascene structure e.g., 16A, to form metal capping layer 20A. The exposed copper portion may optionally include a deposited catalyzing agent such as Pd, deposited by conventional methods. Preferably, the plating solution includes a reducing agent including hypophosphite (H2PO2) and dimethyl amine borane (DMAB). The selectively electroless deposited metal capping layer 20A is formed at a thickness of about 100 Angstroms to about 300 Angstroms to fill the dual damascene to the trench level. An optional annealing process at about 400° C. to about 550° C. is carried out following the electroless deposition process. It will be appreciated that, less preferably, due to additional capacitance contribution, a capping layer, for example, selected from the same materials as the compressive dielectric layers (e.g., 14A and 14B) may be formed by conventional CVD blanket deposition over the planarized dual damascene structure.
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In this embodiment, the compressive dielectric layers 14C and 14D, formed in compressive stress relationship with respect to at least underlying and preferably overlying dielectric insulating layers advantageously additionally serves as an etch stop layer, for example where the trench portion e.g., 16AB is etched through the thickness of the compressive dielectric layers e.g., 14C and into a portion of the underlying insulating dielectric layer e.g., 12A for a predetermined distance e.g., about 50 Angstroms to about 300 Angstroms. By positioning the compressive dielectric layers e.g., 14C and 14D adjacent the trench portion e.g., 16AB and 16BB, the compressive stress of the dielectric layers better offsets (counteracts) tensile stresses present in the overlying and underlying dielectric insulating layers, e.g., 12A and 12B as well as serves as an etch stop layer for more accurately etching a trench portion depth.
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It will be appreciated that the compressive dielectric layers may be formed at about the level of the transition between the trench portion, e.g., 16AB and/or 16BB of the dual damascene structures, e.g., 16A and/or 16B, in either or both the metallization levels Mi and Mi+1 and that the compressive stress dielectric layers, e.g., compressive dielectric layers 14A, 14B, 14C, and 14D in this case may serve as both hardmask layers/compressive dielectric layers in the embodiments shown in
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In process 301 a semiconductor process wafer is provided. In process 303, a first dielectric insulating layer is formed to a first level according to preferred embodiments. In process 305 a compressive dielectric layer is formed according to preferred embodiments. In process 307, a second dielectric insulating layer is formed over the compressive dielectric layer. In process 309 a copper filled dual damascene is formed. In process 311, a selectively deposited metal capping layer is deposited over the copper dual damascene. In process 313, the above processes are repeated to form stacked metallization layers including dual damascenes.
Thus, a dual damascene and metallization layer structure and method for forming the same has been presented for reducing the cumulative effect of stress buildup thereby reducing the incidence of cracking in multi-level integrated circuit devices to improve both yield and reliability, while minimizing an increase in metallization layer capacitance. By forming selectively deposited metal capping layers and forming the compressive dielectric layers at a level of minimum capacitance in a modeled metallization layer without compressive dielectric layers, the addition of the compressive dielectric layers at the determined level minimizes increases to the capacitance of the metallization layer.
The preferred embodiments, aspects, and features of the invention having been described, it will be apparent to those skilled in the art that numerous variations, modifications, and substitutions may be made without departing from the spirit of the invention as disclosed and further claimed below.
