METHOD AND APPARATUS FOR DUAL EDGE MEMORY WRITE OPERATION

Abstract

An apparatus for dual edge memory write operation is provided. The apparatus may include a write enable circuit to receive a write enable signal for writing data to a memory cell, and a write driver circuit to receive a data signal and a complementary data signal, and output a bus signal and a complementary bus signal to the memory cell. The write driver circuit may be coupled to the write enable circuit. The write enable circuit may initiate a write operation to write data to the memory cell based on a falling edge of the write enable signal.

Description

TECHNICAL FIELD

The present disclosure relates generally to memory write operations, and more specifically to memory write operations using rising and falling edges to initiate the write operation.

SUMMARY

According to an aspect of one or more examples, there is provided an apparatus that may include a write enable circuit to receive a write enable signal for writing data to a memory cell, and a write driver circuit to receive a data signal and a complementary data signal, and output a bus signal and a complementary bus signal to the memory cell, wherein the write driver circuit is coupled to the write enable circuit. The write enable circuit may initiate a write operation to write data to the memory cell based on a falling edge of the write enable signal. The write enable circuit may initiate a write operation to write data to the memory cell based on a falling edge of the write enable signal when a supply voltage to the write driver circuit is below a first threshold voltage. The write enable circuit may initiate a write operation to write data to the memory cell based on a rising edge of the write enable signal when a supply voltage to the write driver circuit is above a second threshold voltage. The first threshold voltage may be approximately 0.5 volts and the second threshold voltage may be approximately 0.8 volts.

The write enable circuit may include a first NMOS transistor having a gate terminal to receive the write enable signal, a source terminal, and a drain terminal that is coupled to the source terminal, and a second NMOS transistor having a gate terminal to receive the write enable signal, a source terminal that is coupled to ground, and a drain terminal that is coupled to the drain terminal of the first NMOS transistor. The gate driver circuit may include a first CMOS inverter to receive the data signal and a second CMOS inverter to receive the complementary data signal. The first CMOS inverter may output the complementary bus signal, and the second CMOS inverter may output the bus signal. The write enable circuit may be coupled to the first CMOS inverter to cause the complementary bus signal to be a negative voltage based on the falling edge of the write enable signal. The drain terminal of the first NMOS transistor may be coupled to the drain terminal of the second NMOS transistor, and the drain terminals of the first and second NMOS transistors may be coupled to the first and second CMOS inverters. The first CMOS inverter may include a first PMOS transistor and a third NMOS transistor, and the second CMOS inverter may include a second PMOS transistor and a fourth NMOS transistor. The first PMOS transistor of the first CMOS inverter may include a source terminal coupled to the supply voltage, a gate terminal coupled to the data signal, and a drain terminal coupled to the complimentary bus signal, and the third NMOS transistor of the first CMOS inverter may include a drain terminal coupled to the complementary bus signal, a gate terminal coupled to the data signal, and a source terminal coupled to the write enable circuit. The second PMOS transistor of the second CMOS inverter may include a source terminal coupled to the supply voltage, a gate terminal coupled to the complementary data signal, and a drain terminal coupled to the bus signal, and the fourth NMOS transistor of the second CMOS inverter may include a drain terminal coupled to the bus signal, a gate terminal coupled to the complimentary data signal, and a source terminal coupled to the write enable signal. The drain terminals of the first and second NMOS transistors are coupled to the source terminals of the third and fourth NMOS transistors.

According to an aspect of one or more examples, there is provided a method of writing data to a memory cell. The method may include generating a write enable signal to control writing of data to a memory cell, receiving a data signal and a complementary data signal corresponding to the data to be written to the memory cell, outputting a bus signal and a complementary bus signal based on the write enable signal, the data signal, and the complementary data signal, and storing the data in the memory cell based on a falling edge of the write enable signal. The data may be stored in the memory cell based on a falling edge of the write enable signal when a supply voltage is below a first threshold voltage. The data may be stored in the memory cell based on a rising edge of the write enable signal when a supply voltage is above a second threshold voltage. The method may also include adjusting a pulse width of the write enable signal to control writing data to the memory cell based on the falling edge of the write enable signal. The first threshold voltage may be approximately 0.5 volts and the second threshold voltage may be approximately 0.8 volts. The first threshold voltage may be approximately equal to the second threshold voltage.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 shows a circuit for driving a write operation of a memory cell according to one or more examples.

FIG. 2A shows a timing diagram of various signals according to the operation of the circuit shown in FIG. 1 when a supply voltage is greater than a threshold voltage.

FIG. 2B shows a timing diagram of various signals according to the operation of the circuit shown in FIG. 1 when a supply voltage is less than a threshold voltage.

FIG. 3 shows a circuit diagram of an SRAM memory cell according to one or more examples.

DETAILED DESCRIPTION OF VARIOUS EXAMPLES

Reference will now be made in detail to the following various examples, which are illustrated in the accompanying drawings, wherein like reference numerals refer to like elements throughout. The following examples may be embodied in various forms without being limited to the examples set forth herein.

The present disclosure relates to a write operation for solid state memory devices, such as static random access memory (SRAM). A write operation may rely on a supply voltage that exceeds a certain threshold, e.g., 0.8 volts, in order to write data to a memory cell. However, certain applications require lower supply voltages, e.g., less than 0.5 volts, that may result in write operation failures, particularly at extremely cold temperatures. Therefore, there is a need for an apparatus and method of conducting a write operation at lower supply voltages.

FIG. 1 shows a circuit 100 for driving a write operation of a memory cell according to one or more examples. The example circuit 100 of FIG. 1 includes an SRAM memory 105 that may include a plurality of memory cells 110. Although the example circuit 100 of FIG. 1 is shown using SRAM memory 105, other types of memory may be used. The example circuit 100 may also include a write enable circuit 115 that enables a write operation to write data to the memory cells 110 of the SRAM memory 105. The write enable circuit 115 may receive a write enable signal (WEN) 120 to control a write operation. The example circuit 100 may also include a write driver circuit 125 that is coupled to the write enable circuit 115 and to the SRAM memory 105. The write driver circuit 125 may receive data that is to be written into the SRAM memory 105, and output signals to the SRAM memory 105 based on the write enable signal (WEN) 120.

More specifically, the write driver circuit 125 may receive a data signal (Data) 130 and a complementary data signal (Data_n) 135, and may output a bus signal (Bus) 140 and a complementary bus signal (Bus_n) 145. The bus signal (Bus) 140 and the complementary bus signal (Bus_n) 145 are coupled to a bitline (BL) 150 and a complementary bitline (BLN) 155 for respective groups of memory cells 110 in the SRAM memory 105. The bitline (BL) 150 and complementary bitline (BLN) 155 are coupled to internal nodes Q and Q_n, (e.g., Q 210 and Q_n 215 described in FIGS. 2 and 3) within respective memory cells 110 that store data in respective memory cells 110.

The write driver circuit 125 may include a first CMOS inverter 160 to receive the data signal (Data) 130, and output the complementary bus signal (Bus_n) 145. The first CMOS inverter 160 includes a PMOS transistor P1165 and an NMOS transistor N1170 having respective gate terminals that are configured to receive the data signal (Data) 130. A source terminal of the PMOS transistor P1165 is coupled to a supply voltage V_DD. A drain terminal of the PMOS transistor P1165 is coupled to a drain terminal of the NMOS transistor N1170, which output the complementary bus signal (Bus_n) 145. A source terminal of the NMOS transistor N1170 of the first CMOS inverter 160 is coupled to the write enable circuit 115, as explained further below.

The write driver circuit 125 may also include a second CMOS inverter 175 to receive the complementary data signal (Data_n) 135 and output the bus signal (Bus) 140. The second CMOS inverter 175 includes a PMOS transistor P2180 and an NMOS transistor N2185 having respective gate terminals that are configured to receive the complementary data signal (Data_n) 135. A source terminal of the PMOS transistor P2180 is coupled to the supply voltage V_DD. A drain terminal of the PMOS transistor P2180 is coupled to a drain terminal of the NMOS transistor N2185, which outputs the bus signal (Bus) 140. A source terminal of the NMOS transistor N2185 of the second CMOS inverter 175 is coupled to the write enable circuit 115, and the source terminal of the NMOS transistor N1170 of the first CMOS inverter 160, as explained further below.

The write enable circuit 115 includes a first NMOS transistor 190 and a second NMOS transistor 195 having gate terminals to receive the write enable signal WEN 120. The first NMOS transistor 190 of the write enable circuit 115 includes a drain terminal and a source terminal, which are coupled together. The second NMOS transistor 195 of the write enable circuit 115 includes a source terminal that is coupled to ground or to a second supply voltage V_SS (not shown in FIG. 1) that is less than the supply voltage V_DD. The second NMOS transistor 195 of the write enable circuit 115 includes a drain terminal that is coupled to the drain terminal of the first NMOS transistor 190. The drain terminals of the first and second NMOS transistors 190 and 195 of the write enable circuit 115 are coupled to the source terminals of the NMOS transistors N1, N2170 and 185 of the first and second CMOS inverters 160 and 175.

Operation of the circuit 100 shown in FIG. 1 will be described below with reference to FIGS. 2A and 2B. FIG. 2A shows a timing diagram 200A of various signals according to the operation of the circuit 100 shown in FIG. 1 when the supply voltage V_DD is greater than a threshold voltage according to various examples. FIG. 2B shows a timing diagram 200B of various signals according to the operation of the circuit 100 shown in FIG. 1 when the supply voltage V_DD is less than a threshold voltage according to various examples. According to one or more examples, the threshold may be approximately 0.5 volts, although the threshold may vary. For example, the threshold may be a range of voltages. For example, FIG. 2A may show operation of the circuit 100 of FIG. 1 when the supply voltage V_DD is high, such as approximately 0.8 volts or 0.9 volts, and FIG. 2B may show operation of the circuit 100 of FIG. 1 when the supply voltage V_DD is low, such as approximately 0.4 volts.

FIG. 2A shows a timing diagram 200A of various signals according to the operation of the circuit 100 of FIG. 1 when a supply voltage V_DD is high, for example approximately 0.8 volts. At the rising edge 205 of the write enable signal WEN 120, the data signal (Data) 130 is logic high, and the complementary data signal (Data_n) 135 is logic low. The rising edge 205 of the write enable signal WEN 120 causes the first and second NMOS transistors 190 and 195 of the write enable circuit 115 to turn on, which causes the source terminals of the NMOS transistors N1, N2170 and 185 of the first and second CMOS inverters 160 and 175 to be coupled to ground. The logic high level of the data signal (Data) 130 causes the NMOS transistor N1170 of the first CMOS inverter 160 to turn on, which causes the complementary bus signal (Bus_n) 145 to be at a logic low level. The logic low level of the complementary data signal (Data_n) 135 causes the PMOS transistor P2180 to turn on, which couples the bus signal (Bus) 140 to the supply voltage V_DD, and results in a logic high level. As explained above with reference to FIG. 1, the bus signal (Bus) 140 and the complementary bus signal (Bus_n) 145 are coupled to the bitline (BL) 150 and complementary bitline (BLN) 155 corresponding to respective memory cells 110 within the SRAM memory 105.

FIG. 3 shows a circuit diagram 300 of an SRAM memory cell according to one or more examples. According to one or more examples, the SRAM memory cell may be one of the memory cells 110 described in FIG. 1. As shown in FIG. 3, the respective memory cells 110 include an internal node Q 210 and a complementary internal node Q_n 215 that store the logic high or logic low data in the memory cell 110. As shown in FIG. 2A, the internal node Q 210 becomes a logic high level in response to the bus line signal (Bus) 140 becoming a logic high level, and the complementary internal node Q_n 215 becomes a logic low level in response to the logic low level of the complementary bus signal (Bus_n) 145. Referring to FIG. 3, a wordline (WL) 305 is coupled to access MOSFETs M1 and M2310A and 310B to selectively couple the bitline (BL) 150 and complementary bitline (BLN) 155 to the memory cell 110. The wordline (WL) 305 may be controlled to allow access to the memory cell 110 in coordination with the write enable signal WEN 120. When the wordline (WL) 305 is a logic high level, access MOSFETs M1 and M2310A and 310B turn on, which couples the logic high signal of bitline (BL) 150 to the drain terminals of MOSFETs M3 and M4310C and 310D and the gate terminals of MOSFETs M5 and M6310E and 310F, and couples the logic low signal of complementary bitline (BLN) 155 to the drain terminals of MOSFETs M5, M6310E and 310F and the gate terminals of MOSFETs M3, M4310C and 310D. The bitline (BL) 150 signal causes MOSFET M6310F to turn on and pull the complementary internal node Q_n 215 to a logic low level, and the complementary bitline (BLN) 155 causes MOSFET M3310C to turn on and pull the internal node Q 210 to a logic high level. Therefore, the write operation is successful because the logic high data signal is written to the internal cell node Q 210. The write operation is successful because the difference between bus signal (Bus) 140 and the complementary bus signal (Bus_n) 145 is sufficient to enable the write operation. However, when the power supply V_DD is a low voltage, e.g., 0.4 volts, the difference between the bus signal (Bus) 140 and the complementary bus signal (Bus_n) 145 may not be sufficient to enable a successful write operation.

FIG. 2B shows a timing diagram 200B of various signals according to the operation of the circuit 100 shown in FIG. 1 when a supply voltage V_DD is less than a threshold voltage. For example, the voltage supply associated with FIG. 2B may be approximately 0.4 volts. The timing diagram 200B of FIG. 2B is similar to the timing diagram 200A of FIG. 2A in that at the rising edge 205 of the write enable signal WEN 120, the data signal (Data) 130 is logic high, and the complementary data signal (Data_n) 135 is logic low. The rising edge 205 of the write enable signal WEN 120 causes the first and second NMOS transistors 190 and 195 of the write enable circuit 115 to turn on, which causes the source terminals of the NMOS transistors N1, N2170 and 185 of the first and second CMOS inverters 160 and 175 to be coupled to ground. The logic high level of the data signal (Data) 130 causes the NMOS transistor N1170 of the first CMOS inverter 160 to turn on, which causes the complementary bus signal (Bus_n) 145 to be at a logic low level. The logic low level of the complementary data signal (Data_n) 135 causes the PMOS transistor P2180 to turn on, which couples the bus signal (Bus) 140 to the supply voltage V_DD, and results in a logic high level. The bus signal (Bus) 140 and the complementary bus signal (Bus_n) 145 are coupled to a bitline (BL) 150 and complementary bitline (BLN) 155 corresponding to respective memory cells 110 within the SRAM memory 105, however, unlike the timing diagram 200A of FIG. 2A, the data is not stored in the internal node Q 210 and a complementary internal node Q_n 215 because the voltage difference between the bus signal (Bus) 140 and the complementary bus signal (Bus_n) 145 is insufficient to enable the write operation. However, the falling edge 220 of the write enable signal WEN 120 causes the voltage level of the complementary bus signal (Bus_n) 145 to become negative 225, which increases the difference between the bus signal (Bus) 140 and the complementary bus signal (Bus_n) 145 to a level sufficient to complete the write operation.

More specifically, when the write enable signal WEN 120 transitions from a logic high level to a logic low level, the first and second NMOS transistors 190 and 195 of the write enable circuit 115 turn off. Due to the parasitic capacitance associated with the coupling of the source and drain terminals of the first NMOS transistor 190 of the write enable circuit 115, the voltage at the source terminals of the NMOS transistors N1, N2170 and 185 of the first and second CMOS inverters 160 and 175 becomes negative. Because the bus signal (Bus) 140 is still coupled to the supply voltage V_DD via the PMOS transistor P2180 of the second CMOS inverter 175, the difference between bus signal (Bus) 140 and the complementary bus signal (Bus_n) 145 increases when the complementary bus signal (Bus_n) 145 becomes a negative voltage 225. As shown in FIG. 2B, when the complementary bus signal (Bus_n) 145 becomes a negative voltage 225, the data is written to the internal cell Q 210 and the complementary internal cell Q_n 215. According to one or more examples, the pulse width of the write enable signal WEN 120 may be adjusted to control the speed of the operation. For example, by reducing the pulse width of the write enable signal WEN 120 (i.e., moving the falling edge 220 closer to the rising edge 205), the write operation may be completed more quickly because the negative voltage 225 on the complementary bus line (Bus_n) 145 corresponds to the falling edge 220 of the write enable signal WEN 120.

By using the falling edge 220 of the write enable signal WEN 120, the write operation may be completed during low voltage supply V_DD operation, while the rising edge 205 of the write enable signal WEN 120 may be used to complete a write operation during high voltage supply V_DD operation. Moreover, the write enable circuit 115 according to one or more examples may be compact. For example, the write enable circuit 115 of FIG. 1 may include two NMOS transistors (e.g., first and second NMOS transistors 190 and 195 in FIG. 1), which may be more compact than other write driver circuitry.

Various examples have been disclosed herein, in connection with the above description and the drawings. It will be understood that it would be unduly repetitious to literally describe and illustrate every combination and subcombination of these examples. Accordingly, all examples can be combined in any way or combination, and the present specification, including the drawings, shall be construed to constitute a complete written description of all combinations and subcombinations of the examples described herein, and of the manner and process of making and using them, and shall support claims to any such combination or subcombination.

It will be appreciated by persons skilled in the art that the examples described herein are not limited to what has been particularly shown and described herein above. In addition, unless mention was made above to the contrary, it should be noted that all of the accompanying drawings are not to scale. A variety of modifications and variations are possible in light of the above teachings.

Claims

1. An apparatus comprising: a write enable circuit to receive a write enable signal for writing data to a memory cell; anda write driver circuit to receive a data signal and a complementary data signal, and output a bus signal and a complementary bus signal to the memory cell, wherein the write driver circuit is coupled to the write enable circuit;wherein the write enable circuit is to initiate a write operation to write data to the memory cell based on a falling edge of the write enable signal.

2. The apparatus of claim 1, wherein the write enable circuit is to initiate a write operation to write data to the memory cell based on a falling edge of the write enable signal when a supply voltage to the write driver circuit is below a first threshold voltage.

3. The apparatus of claim 2, wherein the write enable circuit is to initiate a write operation to write data to the memory cell based on a rising edge of the write enable signal when a supply voltage to the write driver circuit is above a second threshold voltage.

4. The apparatus of claim 3, wherein a time at which the data is written to the memory cell based on the falling edge is configurable based on a pulse width of the write enable signal.

5. The apparatus of claim 3, wherein the first threshold voltage is approximately 0.5 volts and the second threshold voltage is approximately 0.8 volts.

6. The apparatus of claim 1, wherein the write enable circuit comprises: a first NMOS transistor having a gate terminal to receive the write enable signal, a source terminal, and a drain terminal that is coupled to the source terminal; anda second NMOS transistor having a gate terminal to receive the write enable signal, a source terminal that is coupled to ground, and a drain terminal that is coupled to the drain terminal of the first NMOS transistor.

7. The apparatus of claim 6, wherein the write driver circuit comprises a first CMOS inverter to receive the data signal and a second CMOS inverter to receive the complementary data signal.

8. The apparatus of claim 7, wherein the first CMOS inverter is to output the complementary bus signal, and the second CMOS inverter is to output the bus signal.

9. The apparatus of claim 8, wherein the write enable circuit is coupled to the first CMOS inverter to cause the complementary bus signal to be a negative voltage based on the falling edge of the write enable signal.

10. The apparatus of claim 9, wherein the drain terminal of the first NMOS transistor is coupled to the drain terminal of the second NMOS transistor, and the drain terminals of the first and second NMOS transistors are coupled to the first and second CMOS inverters.

11. The apparatus of claim 7, wherein the first CMOS inverter comprises a first PMOS transistor and a third NMOS transistor, and the second CMOS inverter comprises a second PMOS transistor and a fourth NMOS transistor.

12. The apparatus of claim 11, wherein the first PMOS transistor of the first CMOS inverter comprises a source terminal coupled to the supply voltage, a gate terminal coupled to the data signal, and a drain terminal coupled to the complementary bus signal, and the third NMOS transistor of the first CMOS inverter comprises a drain terminal coupled to the complementary bus signal, a gate terminal coupled to the data signal, and a source terminal coupled to the write enable circuit.

13. The apparatus of claim 12, wherein the second PMOS transistor of the second CMOS inverter comprises a source terminal coupled to the supply voltage, a gate terminal coupled to the complementary data signal, and a drain terminal coupled to the bus signal, and the fourth NMOS transistor of the second CMOS inverter comprises a drain terminal coupled to the bus signal, a gate terminal coupled to the complementary data signal, and a source terminal coupled to the write enable circuit.

14. The apparatus of claim 13, wherein the drain terminals of the first and second NMOS transistors are coupled to the source terminals of the third and fourth NMOS transistors.

15. A method of writing data to a memory cell, the method comprising: generating a write enable signal to control writing of data to a memory cell;receiving a data signal and a complementary data signal corresponding to the data to be written to the memory cell;outputting a bus signal and a complementary bus signal based on the write enable signal, the data signal, and the complementary data signal;storing the data in the memory cell based on a falling edge of the write enable signal.

16. The method of claim 15, wherein the data is stored in the memory cell based on a falling edge of the write enable signal when a supply voltage is below a first threshold voltage.

17. The method of claim 16, wherein the data is stored in the memory cell based on a rising edge of the write enable signal when a supply voltage is above a second threshold voltage.

18. The method of claim 17, comprising adjusting a pulse width of the write enable signal to control writing data to the memory cell based on the falling edge of the write enable signal.

19. The method of claim 17, wherein the first threshold voltage is approximately 0.5 volts and the second threshold voltage is approximately 0.8 volts. 20 The method of claim 17, wherein the first threshold voltage is approximately equal to the second threshold voltage.