Claims
- 1. A Built-In Self-Test (BIST) circuit for an electronic circuit or system, comprising:
a test bus; a first controller connected to the test bus; and a memory coupled to the first controller, the memory being communicably coupleable to a second controller, wherein the memory is configured to receive first data from the second controller while being communicably coupled to the second controller, and wherein the first controller is configured to fetch the first data from the memory and apply the first data to the electronic circuit or system via the test bus for testing, programming, or debugging the electronic circuit or system, thereby allowing the first data to be applied to the electronic circuit or system independent of the second controller.
- 2. The BIST circuit of claim 1 wherein the first controller includes an interface compatible with the IEEE 1149.1 test standard, the first controller being further configured to apply the first data to the electronic circuit or system via the test bus using the protocol given in the IEEE 1149.1 test standard.
- 3. The BIST circuit of claim 1 wherein the test bus comprises a plurality of test buses, the plurality of test buses including a first digital test bus and a second digital test bus, the first digital test bus being configured to convey test signals compatible with the IEEE 1149.1 test standard.
- 4. The BIST circuit of claim 1 wherein the memory is configured to receive at least one scan vector from the second controller, the first controller being configured to fetch the at least one scan vector from the memory and apply the at least one scan vector to the electronic circuit or system, thereby allowing the at least one scan vector to be applied to the electronic circuit or system independent of the second controller.
- 5. The BIST circuit of claim 1 wherein the first controller is further configured to receive resultant data from the electronic circuit or system in response to testing, programming, or debugging the electronic circuit or system.
- 6. The BIST circuit of claim 5 wherein the first controller is configured to fetch expected data from the memory, the expected data being indicative of the resultant data expected to be received from the electronic circuit or system in response to being tested, programmed, or debugged.
- 7. The BIST circuit of claim 6 wherein the first controller is further configured to fetch mask data from the memory, the mask data being operative to mask at least a portion of the expected data.
- 8. The BIST circuit of claim 6 wherein the first controller is configured to receive actual data from the electronic circuit or system in response to being tested, programmed, or debugged, the first controller further including a compare circuit configured to compare the actual data to the expected data to determine whether the actual data matches the expected data.
- 9. The BIST circuit of claim 8 wherein the memory is configured to receive at least one scan vector from the second controller, the first controller being configured, in the event it is determined the actual data does not match the expected data, to fetch at least one clean-up vector from the memory and apply the at least one clean-up vector to the electronic circuit or system.
- 10. A method of testing, programming, or debugging an electronic circuit or system having a Built-In Self-Test (BIST) circuit, comprising the steps of:
providing a test bus; providing a first controller connected to the test bus; providing a memory coupled to the first controller, the memory being communicably coupleable to a second controller; receiving first data from the second controller by the memory while the memory is communicably coupled to the second controller; fetching the first data from the memory by the first controller; and applying the first data to the electronic circuit or system via the test bus by the first controller for testing, programming, or debugging the electronic circuit or system, the first data being applied to the electronic circuit or system independent of the second controller.
- 11. The method of claim 10 wherein the applying step includes applying the first data to the electronic circuit or system via the test bus by the first controller using the protocol given in the IEEE 1149.1 test standard.
- 12. The method of claim 10 wherein the receiving step includes receiving at least one scan vector from the second controller by the memory, the fetching step includes fetching the at least one scan vector from the memory by the first controller, and the applying step includes applying the at least one scan vector to the electronic circuit or system by the first controller, the at least one scan vector being applied to the electronic circuit or system independent of the second controller.
- 13. The method of claim 12 wherein the receiving step includes receiving and storing a plurality of scan vectors from the second controller by the memory, the plurality of scan vectors including at least one reused scan vector, the at least one reused scan vector being stored at one or more predetermined locations of the memory.
- 14. The method of claim 13 wherein the fetching step includes fetching the at least one reused scan vector from the one or more predetermined locations of the memory by the first controller, and the applying step includes applying the at least one reused scan vector to the electronic circuit or system by the first controller.
- 15. The method of claim 14 further including the step of determining whether a compare condition is asserted by the first controller, and wherein the applying step includes, in the event the compare condition is asserted, applying the at least one reused scan vector to the electronic circuit or system by the first controller.
- 16. The method of claim 12 further including the steps of receiving a first input signal and a second input signal by the first controller, the first input signal being indicative of a predetermined location of the memory where the at least one scan vector is stored, determining whether the second input signal is asserted by the first controller, and wherein the applying step includes, in the event the second input signal is asserted, applying the at least one scan vector stored at the predetermined location of the memory to the electronic circuit or system by the first controller.
- 17. The method of claim 16 wherein the receiving step includes receiving at least one clean-up vector from the second controller by the memory, the fetching step includes fetching the at least one clean-up vector from the memory by the first controller, and the applying step includes, in the event the second input signal is de-asserted, applying the at least one clean-up vector to the electronic circuit or system by the first controller.
- 18. The method of claim 10 further including the step of receiving resultant data from the electronic circuit or system by the first controller in response to testing, programming, or debugging the electronic circuit or system.
- 19. The method of claim 18 wherein the first receiving step includes receiving predetermined informational data associated with the first data from the second controller by the memory, the fetching step including fetching the first data and the associated predetermined informational data from the memory by the first controller.
- 20. The method of claim 19 further including the step of providing an indication of at least a portion of the predetermined informational data by the first controller based on the resultant data received from the electronic circuit or system.
- 21. The method of claim 18 wherein the fetching step includes fetching expected data from the memory by the first controller, the expected data being indicative of the resultant data expected to be received from the electronic circuit or system in response to being tested, programmed, or debugged.
- 22. The method of claim 21 wherein the fetching step further includes fetching mask data from the memory by the first controller, the mask data being operative to mask at least a portion of the expected data.
- 23. The method of claim 21 wherein the second receiving step includes receiving actual data from the electronic circuit or system by the first controller in response to being tested, programmed, or debugged, the method further including the step of comparing the actual data to the expected data by the first controller to determine whether the actual data matches the expected data.
- 24. The method of claim 23 wherein the first receiving step includes receiving at least one scan vector from the second controller by the memory, the fetching step including, in the event it is determined the actual data does not match the expected data, fetching at least one clean-up vector from the memory by the first controller, and the applying step including applying the at least one clean-up vector to the electronic circuit or system by the first controller.
- 25. The method of claim 24 wherein the applying step includes applying at least one scan vector to the electronic circuit or system by the first controller, the at least one scan vector being operative to start a current scan operation, and the applying step including applying the at least one clean-up vector to the electronic circuit or system by the first controller when the current scan operation is finished.
CROSS REFERENCE TO RELATED APPLICATIONS
[0001] This application claims priority of U.S. Provisional Patent Application No. 60/336,586 filed Dec. 4, 2001 entitled METHOD AND APPARATUS FOR EMBEDDED BUILT-IN SELF-TEST (BIST) OF ELECTRONIC CIRCUITS AND SYSTEMS.
Provisional Applications (1)
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Number |
Date |
Country |
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60336586 |
Dec 2001 |
US |