Control logic

Industry

CPC
G01R31/318555

This industry / category may be too specific. Please go to a parent level for more data

Parent Industries

GPHYSICS G01Measuring instruments G01RMEASURING ELECTRIC VARIABLES MEASURING MAGNETIC VARIABLES G01R31/00Arrangements for testing electric properties Arrangements for locating electric faults Arrangements for electrical testing characterised by what is being tested not provided for elsewhere

Current Industry

G01R31/318555Control logic

Industries

Please log in for detailed analytics

Patents Grantslast 30 patents

Information Patent Grant
Test access port with address and command capability
- Patent number 12,188,980
- Issue date Jan 7, 2025
- Texas Instruments Incorporated
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Grant
At-speed test access port operations
- Patent number 12,181,521
- Issue date Dec 31, 2024
- Texas Instruments Incorporated
- Lee D. Whetsel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
3D tap and scan port architectures
- Patent number 12,164,001
- Issue date Dec 10, 2024
- Texas Instruments Incorporated
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Grant
TVF transition coverage with self-test and production-test time red...
- Patent number 12,146,911
- Issue date Nov 19, 2024
- STMICROELECTRONICS INTERNATIONAL N.V.
- Venkata Narayanan Srinivasan
- G01 - MEASURING TESTING
Information Patent Grant
Reconfigurable JTAG architecture for implementation of programmable...
- Patent number 12,123,912
- Issue date Oct 22, 2024
- University of Florida Research Foundation, Incorporated
- Swarup Bhunia
- G01 - MEASURING TESTING
Information Patent Grant
System and method for access control of a plurality of instruments...
- Patent number 12,111,356
- Issue date Oct 8, 2024
- Erik Larsson
- G01 - MEASURING TESTING
Information Patent Grant
Scan compression through pin data encoding
- Patent number 12,105,145
- Issue date Oct 1, 2024
- STMICROELECTRONICS INTERNATIONAL N.V.
- Sandeep Jain
- G01 - MEASURING TESTING
Information Patent Grant
Multiplexer for SDFQ having differently-sized scan and data transis...
- Patent number 12,099,090
- Issue date Sep 24, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd
- Huaixin Xian
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Emulation of JTAG/SCAN test interface protocols using SPI communica...
- Patent number 12,092,690
- Issue date Sep 17, 2024
- SILICONCH SYSTEMS PVT LTD
- Rakesh Kumar Polasa
- G01 - MEASURING TESTING
Information Patent Grant
In system test of chips in functional systems
- Patent number 12,078,678
- Issue date Sep 3, 2024
- NVIDIA Corporation
- Shantanu Sarangi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Wrapper cell design and built-in self-test architecture for 3DIC te...
- Patent number 12,066,490
- Issue date Aug 20, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd
- Anshuman Chandra
- G01 - MEASURING TESTING
Information Patent Grant
Scan flip-flops with pre-setting combinational logic
- Patent number 12,066,489
- Issue date Aug 20, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd
- Johnny Chiahao Li
- G01 - MEASURING TESTING
Information Patent Grant
Test access port architecture to facilitate multiple testing modes
- Patent number 12,057,183
- Issue date Aug 6, 2024
- Micron Technology, Inc.
- Michael Richard Spica
- G11 - INFORMATION STORAGE
Information Patent Grant
3D stacked die testing structure
- Patent number 12,055,586
- Issue date Aug 6, 2024
- Cadence Design Systems, Inc.
- Sagar Kumar
- G01 - MEASURING TESTING
Information Patent Grant
Addressable test access port
- Patent number 12,050,247
- Issue date Jul 30, 2024
- Texas Instruments Incorporated
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Grant
Method of testing a stacked integrated circuit device
- Patent number 12,032,021
- Issue date Jul 9, 2024
- Graphcore Limited
- Stephen Felix
- G01 - MEASURING TESTING
Information Patent Grant
Power-sensitive scan-chain testing
- Patent number 12,025,661
- Issue date Jul 2, 2024
- MARVELL ASIA PTE. LTD.
- Balaji Upputuri
- G01 - MEASURING TESTING
Information Patent Grant
3D stacked die test architecture
- Patent number 12,007,441
- Issue date Jun 11, 2024
- Texas Instruments Incorporated
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Grant
Scan correlation-aware scan cluster reordering method and apparatus...
- Patent number 12,000,891
- Issue date Jun 4, 2024
- UIF (University Industry Foundation), Yonsei University
- Sungho Kang
- G01 - MEASURING TESTING
Information Patent Grant
Interface system for interconnected die and MPU and communication m...
- Patent number 11,971,446
- Issue date Apr 30, 2024
- Jinghe Wei
- G01 - MEASURING TESTING
Information Patent Grant
Dummy dual in-line memory module (DIMM) testing system based on bou...
- Patent number 11,965,931
- Issue date Apr 23, 2024
- INVENTEC (PUDONG) TECHNOLOGY CORPORATION
- Yuan Sang
- G01 - MEASURING TESTING
Information Patent Grant
Shadow access port method and apparatus
- Patent number 11,906,582
- Issue date Feb 20, 2024
- Texas Instruments Incorporated
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Grant
Joint test action group transmission system capable of transmitting...
- Patent number 11,892,508
- Issue date Feb 6, 2024
- Realtek Semiconductor Corp.
- Chen-Tung Lin
- G01 - MEASURING TESTING
Information Patent Grant
Integrated circuit, test assembly and method for testing an integra...
- Patent number 11,874,325
- Issue date Jan 16, 2024
- Infineon Technologies AG
- Tobias Kilian
- G01 - MEASURING TESTING
Information Patent Grant
Reduced signaling interface method and apparatus
- Patent number 11,867,756
- Issue date Jan 9, 2024
- Texas Instruments Incorporated
- Lee D. Whetsel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrated circuit chip testing interface with reduced signal wires
- Patent number 11,860,228
- Issue date Jan 2, 2024
- Xilinx, Inc.
- Albert Shih-Huai Lin
- G01 - MEASURING TESTING
Information Patent Grant
Device testing architecture, method, and system
- Patent number 11,846,673
- Issue date Dec 19, 2023
- Texas Instruments Incorporated
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Grant
Multiplexer for SDFQ having differently-sized scan and data transis...
- Patent number 11,821,947
- Issue date Nov 21, 2023
- Taiwan Semiconductor Manufacturing Company, Ltd
- Huaixin Xian
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
AT-speed test access port operations
- Patent number 11,808,810
- Issue date Nov 7, 2023
- Texas Instruments Incorporated
- Lee D. Whetsel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Scan testing in a processor
- Patent number 11,802,911
- Issue date Oct 31, 2023
- Graphcore Limited
- Natalie Narkonski
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
SCAN-TESTABLE ELECTRONIC CIRCUIT AND CORRESPONDING METHOD OF TESTIN...
- Publication number 20240426908
- Publication date Dec 26, 2024
- STMicroelectronics International N.V.
- Andrea Floridia
- G01 - MEASURING TESTING
Information Patent Application
LOGIC BIST CIRCUIT AND SEMICONDUCTOR DEVICE INCLUDING SAME
- Publication number 20240426909
- Publication date Dec 26, 2024
- SAMSUNG ELECTRONICS CO,. LTD.
- Sangsoon IM
- G01 - MEASURING TESTING
Information Patent Application
TVF TRANSITION COVERAGE WITH SELF-TEST AND PRODUCTION-TEST TIME RED...
- Publication number 20240402249
- Publication date Dec 5, 2024
- STMicroelectronics International N.V.
- Venkata Narayanan Srinivasan
- G01 - MEASURING TESTING
Information Patent Application
ADDRESSABLE TEST ACCESS PORT
- Publication number 20240385244
- Publication date Nov 21, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Application
MULTIPLEXER FOR SDFQ HAVING DIFFERENTLY-SIZED SCAN AND DATA TRANSIS...
- Publication number 20240369629
- Publication date Nov 7, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Huaixin XIAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Wrapper Cell Design and Built-In Self-Test Architecture for 3DIC Te...
- Publication number 20240361385
- Publication date Oct 31, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Anshuman Chandra
- G01 - MEASURING TESTING
Information Patent Application
Scan Flip-Flops With Pre-Setting Combinational Logic
- Publication number 20240361383
- Publication date Oct 31, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Johnny Chiahao Li
- G01 - MEASURING TESTING
Information Patent Application
3D STACKED DIE TEST ARCHITECTURE
- Publication number 20240319274
- Publication date Sep 26, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Application
EMULATION OF JTAG/SCAN TEST INTERFACE PROTOCOLS USING SPI COMMUNICA...
- Publication number 20240219464
- Publication date Jul 4, 2024
- SILICONCH SYSTEMS PVT LTD
- Rakesh Kumar POLASA
- G01 - MEASURING TESTING
Information Patent Application
MULTIPLE ACCESS PORT CIRCUITS
- Publication number 20240183903
- Publication date Jun 6, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Application
Scan Flip-Flops With Pre-Setting Combinational Logic
- Publication number 20240077534
- Publication date Mar 7, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Johnny Chiahao Li
- G01 - MEASURING TESTING
Information Patent Application
SYSTEM AND METHOD FOR ACCESS CONTROL OF A PLURALITY OF INSTRUMENTS...
- Publication number 20240061041
- Publication date Feb 22, 2024
- Erik Larsson
- G01 - MEASURING TESTING
Information Patent Application
AT-SPEED TEST ACCESS PORT OPERATIONS
- Publication number 20240061038
- Publication date Feb 22, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND SYSTEM FOR TESTING SEMICONDUCTOR CIRCUITS
- Publication number 20240003972
- Publication date Jan 4, 2024
- Ampere Computing LLC
- Kha NGUYEN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
3D TAP & SCAN PORT ARCHITECTURES
- Publication number 20230417831
- Publication date Dec 28, 2023
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Application
MULTIPLEXER FOR SDFQ HAVING DIFFERENTLY-SIZED SCAN AND DATA TRANSIS...
- Publication number 20230408582
- Publication date Dec 21, 2023
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Huaixin XIAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTERFACE/UNICAST FOR TEST CONTENT, FIRMWARE, AND SOFTWARE DELIVERY
- Publication number 20230408581
- Publication date Dec 21, 2023
- Intel Corporation
- Rakesh Kandula
- G01 - MEASURING TESTING
Information Patent Application
ADDRESSABLE TEST ACCESS PORT
- Publication number 20230400513
- Publication date Dec 14, 2023
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Application
SCAN COMPRESSION THROUGH PIN DATA ENCODING
- Publication number 20230375617
- Publication date Nov 23, 2023
- STMicroelectronics International N.V.
- Sandeep Jain
- G01 - MEASURING TESTING
Information Patent Application
INTEGRATED CIRCUIT CHIP TESTING INTERFACE WITH REDUCED SIGNAL WIRES
- Publication number 20230366929
- Publication date Nov 16, 2023
- Xilinx, Inc.
- Albert Shih-Huai LIN
- G01 - MEASURING TESTING
Information Patent Application
Wrapper Cell Design and Built-In Self-Test Architecture for 3DIC Te...
- Publication number 20230366930
- Publication date Nov 16, 2023
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Anshuman Chandra
- G01 - MEASURING TESTING
Information Patent Application
IN SYSTEM TEST OF CHIPS IN FUNCTIONAL SYSTEMS
- Publication number 20230349970
- Publication date Nov 2, 2023
- NVIDIA Corporation
- Shantanu Sarangi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FALLING CLOCK EDGE JTAG BUS ROUTERS
- Publication number 20230333163
- Publication date Oct 19, 2023
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Application
TEST ACCESS PORT WITH ADDRESS AND COMMAND CAPABILITY
- Publication number 20230333159
- Publication date Oct 19, 2023
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Application
SHADOW ACCESS PORT METHOD AND APPARATUS
- Publication number 20230194603
- Publication date Jun 22, 2023
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Application
AT-SPEED TEST ACCESS PORT OPERATIONS
- Publication number 20230194604
- Publication date Jun 22, 2023
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
WAFER SCALE TESTING USING A 2 SIGNAL JTAG INTERFACE
- Publication number 20230160959
- Publication date May 25, 2023
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
3D TAP & SCAN PORT ARCHITECTURES
- Publication number 20230160958
- Publication date May 25, 2023
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Application
SCAN CORRELATION-AWARE SCAN CLUSTER REORDERING METHOD AND APPARATUS...
- Publication number 20230125568
- Publication date Apr 27, 2023
- UIF (UNIVERSITY INDUSTRY FOUNDATION), YONSEI UNIVERSITY
- Sung Ho KANG
- G01 - MEASURING TESTING
Information Patent Application
Stacked Integrated Circuit Device
- Publication number 20230116320
- Publication date Apr 13, 2023
- Graphcore Limited
- Stephen FELIX
- H01 - BASIC ELECTRIC ELEMENTS

Control logic

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Test access port with address and command capability

At-speed test access port operations

3D tap and scan port architectures

TVF transition coverage with self-test and production-test time red...

Reconfigurable JTAG architecture for implementation of programmable...

System and method for access control of a plurality of instruments...

Scan compression through pin data encoding

Multiplexer for SDFQ having differently-sized scan and data transis...

Emulation of JTAG/SCAN test interface protocols using SPI communica...

In system test of chips in functional systems

Wrapper cell design and built-in self-test architecture for 3DIC te...

Scan flip-flops with pre-setting combinational logic

Test access port architecture to facilitate multiple testing modes

3D stacked die testing structure

Addressable test access port

Method of testing a stacked integrated circuit device

Power-sensitive scan-chain testing

3D stacked die test architecture

Scan correlation-aware scan cluster reordering method and apparatus...

Interface system for interconnected die and MPU and communication m...

Dummy dual in-line memory module (DIMM) testing system based on bou...

Shadow access port method and apparatus

Joint test action group transmission system capable of transmitting...

Integrated circuit, test assembly and method for testing an integra...

Reduced signaling interface method and apparatus

Integrated circuit chip testing interface with reduced signal wires

Device testing architecture, method, and system

Multiplexer for SDFQ having differently-sized scan and data transis...

AT-speed test access port operations

Scan testing in a processor

Patents Applicationslast 30 patents

SCAN-TESTABLE ELECTRONIC CIRCUIT AND CORRESPONDING METHOD OF TESTIN...

LOGIC BIST CIRCUIT AND SEMICONDUCTOR DEVICE INCLUDING SAME

TVF TRANSITION COVERAGE WITH SELF-TEST AND PRODUCTION-TEST TIME RED...

ADDRESSABLE TEST ACCESS PORT

MULTIPLEXER FOR SDFQ HAVING DIFFERENTLY-SIZED SCAN AND DATA TRANSIS...

Wrapper Cell Design and Built-In Self-Test Architecture for 3DIC Te...

Scan Flip-Flops With Pre-Setting Combinational Logic

3D STACKED DIE TEST ARCHITECTURE

EMULATION OF JTAG/SCAN TEST INTERFACE PROTOCOLS USING SPI COMMUNICA...

MULTIPLE ACCESS PORT CIRCUITS

Scan Flip-Flops With Pre-Setting Combinational Logic

SYSTEM AND METHOD FOR ACCESS CONTROL OF A PLURALITY OF INSTRUMENTS...

AT-SPEED TEST ACCESS PORT OPERATIONS

METHOD AND SYSTEM FOR TESTING SEMICONDUCTOR CIRCUITS

3D TAP & SCAN PORT ARCHITECTURES

MULTIPLEXER FOR SDFQ HAVING DIFFERENTLY-SIZED SCAN AND DATA TRANSIS...

INTERFACE/UNICAST FOR TEST CONTENT, FIRMWARE, AND SOFTWARE DELIVERY

ADDRESSABLE TEST ACCESS PORT

SCAN COMPRESSION THROUGH PIN DATA ENCODING

INTEGRATED CIRCUIT CHIP TESTING INTERFACE WITH REDUCED SIGNAL WIRES

Wrapper Cell Design and Built-In Self-Test Architecture for 3DIC Te...

IN SYSTEM TEST OF CHIPS IN FUNCTIONAL SYSTEMS

FALLING CLOCK EDGE JTAG BUS ROUTERS

TEST ACCESS PORT WITH ADDRESS AND COMMAND CAPABILITY

SHADOW ACCESS PORT METHOD AND APPARATUS

AT-SPEED TEST ACCESS PORT OPERATIONS

WAFER SCALE TESTING USING A 2 SIGNAL JTAG INTERFACE

3D TAP & SCAN PORT ARCHITECTURES

SCAN CORRELATION-AWARE SCAN CLUSTER REORDERING METHOD AND APPARATUS...

Stacked Integrated Circuit Device