Claims
- 1. A method for manufacturing an integrated circuit, comprising:forming a layer of material on a wafer substrate; and polishing the wafer in a chemical mechanical planarization apparatus for a period of time dependent upon a measurement of chemical bonding of polymer chains within a pad attached to the chemical mechanical planarization apparatus.
CROSS-REFERENCE TO RELATED APPLICATION
This application is a divisional of pending U.S. patent application Ser. No. 08/914,994, filed Aug. 20, 1997 now U.S. Pat. No. 6,114,706, which is a divisional of 08/386,023 filed Feb. 9, 1995 and issued Dec. 16, 1997 as U.S. Pat. No. 5,698,455.
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