Patent Application
20130293256
The present disclosure generally relates to semiconductor processes for fabricating high-voltage integrated circuits with programmable electrical connections.
A common type of integrated circuit (IC) device is a metal-oxide-semiconductor field effect transistor (MOSFET). A MOSFET is a field-effect device that includes a source region, a drain region, a channel region extending between the source and drain regions, and a gate provided over the channel region. The gate includes a conductive gate structure disposed over the channel region. The conductive gate is typically insulated from the channel region by a thin oxide layer.
High-voltage, field-effect transistors (HVFETs) are also well known in the semiconductor arts. Many HVFETs employ a device structure that includes an extended drain region that supports or “blocks” the applied high-voltage (e.g., 200 volts or more) when the device is in the “off” state. Conventional HVFETs are commonly formed as lateral or vertical device structures. In a lateral HVFET, current flow in the on-state is horizontal or substantially parallel to a surface of the semiconductor substrate. On the other hand, in a vertical HVFET current flows vertically through the semiconductor material, e.g., from a top surface of the substrate where the source region is disposed, down to the bottom of the substrate where the drain region is located.
Conventional power IC devices often employ a large vertical or lateral high-voltage output transistor in a configuration wherein the drain of the output transistor is coupled directly to an external pin. The power IC device typically includes a controller circuit that is separate from the high-voltage output transistor. Both the controller and output transistor are usually housed in the same IC package. To provide start-up current for the controller circuit of the IC, a high external voltage may be applied to the external pin. The controller is typically limit-protected from the high externally-applied voltage by a junction field-effect transistor (JFET) “tap” structure. For example, when the drain of the high voltage output transistor is taken to, say 550V, the tap transistor limits the maximum voltage coupled to the controller to approximately 50V, thereby providing a small (2-3 mA) current for start-up of the device. By way of further background, U.S. Pat. No. 7,002,398 discloses a three-terminal JFET transistor that operates in this manner.
The operating characteristics of a power IC device is typically set or programmed by selectively opening (or closing) one or more electrical connections. A zener diode is one type of electrical element used to trim or program analog parameters (e.g., frequency) of a power IC device. A zener diode provides a normally off or non-conducting electrical connection. To change the conducting state of the zener element a high voltage (>10V) is typically applied to breakdown the zener, with the large resulting current (150-200 mA) shorting the anode and cathode terminals of the zener permanently. The cumulative current flowing through the zener elements may be used to program one or more analog parameters. For example, based on the state of one or more zener elements, an analog parameter such as frequency may be set within a specified tolerance in the controller section of the power IC.
The present invention is illustrated by way of example, and not limitation, in the figures of the accompanying drawings, wherein:
A novel integrated anti-fuse device structure for use with a new trimming technology is disclosed. In the following description specific details are set forth, such as material types, voltages, structural features, manufacturing steps, etc., in order to provide a thorough understanding of the disclosure herein. However, persons having ordinary skill in the relevant arts will appreciate that these specific details may not be needed to practice the embodiments described. References throughout this description to “one embodiment”, “an embodiment”, “one example” or “an example” means that a particular feature, structure or characteristic described in connection with the embodiment or example is included in at least one embodiment. The phrases “in one embodiment”, “in an embodiment”, “one example” or “an example” in various places throughout this description are not necessarily all referring to the same embodiment or example. Furthermore, the particular features, structures or characteristics may be combined in any suitable combinations and/or sub-combinations in one or more embodiments or examples.
It should be understood that the elements in the figures are representational, and are not drawn to scale in the interest of clarity. It is also appreciated that although an IC utilizing mostly N-channel transistor devices (both high-voltage and low-voltage) are disclosed. P-channel transistors may also be fabricated by utilizing the opposite conductivity types for all of the appropriate doped regions.
In the context of the present application a high-voltage or power transistor is any semiconductor transistor structure that is capable of supporting 150V or more in an “off” state or condition. In one embodiment, a power transistor is illustrated as an N-channel metal oxide semiconductor field-effect transistor (MOSFET) with the high-voltage being supported between the source and drain regions. In other embodiments, a power transistor may comprise a bipolar junction transistor (BJT), an insulated gate field effect transistor (IGFET), or other device structures that provide a transistor function.
For purposes of this disclosure, “ground” or “ground potential” refers to a reference voltage or potential against which all other voltages or potentials of a circuit or IC are defined or measured. A “pin” provides a point of external electrical connection to an IC device or package, thereby allowing external components, circuits, signals, power, loads, etc., to be coupled to the internal components and circuitry of the power IC device.
In the context of the present disclosure a tap transistor is a three terminal (Le., electrode) transistor device structure in which a voltage at a first or tap terminal is substantially proportional to an applied voltage across the second and third terminals when the applied voltage is less than a pinch-off voltage of the transistor device. When the applied voltage across the second and third terminals exceeds the pinch-off voltage, the voltage provided at the tap terminal is substantially constant or unchanging with increased applied voltage. In one embodiment, a tap transistor comprises a junction field-effect transistor (JFET).
Furthermore, in the context of the present disclosure, an anti-fuse is a circuit element that provides a normally open electrical connection in a device structure like that of a capacitor, with two or more layers of metal, polysilicon, or doped semiconductor material separated by a dielectric layer (e.g., oxide, nitride, etc.). The electrical connection between the two layers of metal can be permanently closed by applying a large voltage across the metal conductors which acts to break down or destroys the dielectric layer, thereby electrically shorting the two metal layers.
The conceptual block diagram of
Prior to programming, anti-fuse structure 20 does not pass any current; that is, it appears as an open circuit to a normal D.C. operating voltage (e.g., VDD=5-6V). Anti-fuse structure 20 may be programmed (i.e., trimmed) by applying a high voltage pulse across terminals 21 and 22 (e.g., 30-35V, 0.5-1.0 mA for 2-5 ms). The voltage required to blow the anti-fuse will depend on the gate oxide thickness (e.g., ˜30V for 25 nm oxide). Application of such a high-voltage pulse causes gate oxide 26 to rupture, resulting in a permanent short between electrodes 21 & 22 with a resistance typically on the order of a few thousand ohms. The state of anti-fuse structure 20 can then be read by sensing its resistance. As will be described in detail below, the trimming pulse utilized to trim the anti-fuse structure is provided externally through the drain pin which connects to the high-voltage output MOSFET device.
Practitioners in the art will appreciate that the amount of current required to trim anti-fuse structure 20 is significantly smaller as compared to existing zener diodes, which normally require >150 mA. Additionally, persons of skill in the art will understand that the integrated anti-fuse device structures disclosed herein may reduce the overall size of the trimming block of a power IC device by a factor of about five or more as compared to prior art designs.
In the embodiment of
In the example of
When the high-voltage pulse is applied across the selected anti-fuse 32, the gate oxide separating the two terminals or capacitive plates ruptures, thereby programming (shorting) the anti-fuse structure.
For the unselected anti-fuses 32—i.e., the ones that are not intended to be blown or shorted—the gate of the corresponding MOSFET 33 is grounded such that MOSFET 33 is off. Consequently, the voltage appearing at the bottom capacitive plate (connected to the drain of MOSFET 33) rises in potential, substantially tracking that of the top plate (connected to node 36). Hence, the gate oxides of the unselected anti-fuses 32 are not ruptured and the device structures remain open circuits.
The state of each anti-fuse programming element 31 may be read at the startup of the power supply, which normally occurs when the VDD power supply line of the controller section of the IC is first charged. Voltage regulator 44 is turned on at that point so that the maximum voltage at node 43 is regulated, e.g., under 12V. To read the programming state of the array of elements 31 which comprise block 30, the drain pin (VEXTERNAL) is raised to greater than about 10V, isolation unit 45 is turned on, and a small current (several microamperes) is pulled through each of the read/write blocks 34. If a particular anti-fuse 32 is programmed, the source of the associated trimming MOSFET 33 (labeled “AFHn”) floats up to the gate-to-source voltage (Vgs) minus the threshold voltage (Vt) of MOSFET 33. On the other hand, if the particular anti-fuse 32 is untrimmed or open, the source of the associated MOSFET 33 is at ground potential. The state of each anti-fuse programming element 31 is latched in the corresponding R/W block 34 when the VDD voltage potential crosses a certain value (˜5V). Thereafter, isolation unit 45 is turned off, thereby isolating node 36 from node 43, and no current flows through anti fuses 32 under the normal operating condition of the power IC.
In one implementation, MOSFET 33 is designed to have a breakdown voltage of approximately 50V, whereas gate oxide 49 of the capacitive anti-fuse structure is manufactured to have a breakdown voltage of about 30V.
The device structure of
As can be seen, P-type buried regions 53 and 54 do not extend laterally beneath thin oxide layers 51 or 49. In one embodiment, a deep implant (not shown) or any other type of equivalent structure may be used to electrically connect each of buried regions 53 & 54. This allows P-type buried regions 53 and 54 which comprise the gate of the JFET to be electrically connected (along with source electrode 58) to a potential at or near ground when anti-fuse programming element 31 is intended to be left untrimmed or open.
Node 43 is also shown connected to the source of PMOS HV transistor 78 (labeled P1) and to one end of resistor 74 of isolation unit 45. The other end of resistor 74 (node 75) is shown connected to the gate of transistor 78, and also to the drain of HV transistor 76 (labeled N2). The drain of PMOS HV transistor 78 is coupled to one end of resistor 79 at node 36. The other end of resistor 79 is coupled to the drain of HV transistor 77 (labeled N3). The sources of transistors 76 & 77 are coupled to ground.
Practitioners will appreciate that PMOS HV transistor 78 of isolation unit 45 functions to isolate anti fuse block 30 from tap transistor 41 under normal operating conditions. Transistor 76 (N2) and resistor 74 function to level shift the gate control signal of PMOS HV transistor 78. In one implementation, the current through transistor 76 and resistor 74 may be designed such that when the transistor 76 is turned on, the gate-to-source voltage of PMOS HV transistor 78 is limited to about 10V. In certain embodiments, the gate of transistor 78 may be clamped.
It should be understood that transistor 77 (N3) and resistor 79 are optional, and may be used to connect anti-fuse structures 32 to ground. In alternative embodiments, transistor 77 (N3) and resistor 79 may be eliminated so that anti-fuse structures 32 are left floating during normal operation.
In one embodiment, isolation unit 45, voltage regulator 44 and trimming MOSFETs 33a-33n (labeled AFH1-AFHn) are should be capable of withstanding the maximum tap voltage (˜50V). For example, the circuit components labeled as high-voltage (HV) devices in
As discussed above, voltage regulator 44 of
Continuing with the example of
To program an individual bit of block 30, the read/write signal line coupled to the gate of the corresponding LV MOSFET 82 is connected to VDD (˜6V) so that the source of associated trimming MOSFET 33 is effectively shorted to ground. The gates of all of the other LV MOSFETs are connected to ground, thereby turning these transistors off. By way of example, to program anti-fuse 32a, the gate of the LV MOSFET 82a is taken to VDD, and the gates of MOSFETs 82b-82n are grounded.
To read the programming state of anti-fuse block 30, the read/write signal coupled to transistors 82 is fed from a current mirror such that each of the LV MOSFETs have few microamps flowing through them.
The example of
By way of example, the parasitic PMOS transistor utilized as a soft HV clamp may have a threshold voltage (Vt) of ˜20V and a BV similar to that of PMOS HV transistor 78, e.g., 55-60V. The gate of the parasitic PMOS transistor may be connected to ground potential. During programming, when node 36 of anti fuse block 30 goes higher than the threshold voltage of the parasitic PMOS transistor, soft clamp element 80 begins flowing a small current, e.g., a few microamperes. For the particular anti-fuse which is being programmed this current will be added to the trim current that flows through the anti-fuse (500 uA-1 mA). For the remaining group of unselected anti-fuses, this low current charges the bottom capacitive plate, thereby reducing the voltage build-up across each of the unselected anti-fuses. During read cycle, the voltage at node 36 does not exceed ˜12V, so each of soft clamp elements 80a-80n is off.
It is further appreciated that the gate capacitance of transistor 62 is substantially lower as compared to the capacitance of anti-fuse 32 due to the relative thickness of field oxide layer 66. In one embodiment, the threshold voltage of transistor 62, which is largely determined by the thickness of field oxide layer 66, is approximately 15-20V. The drain-to-source breakdown voltage of transistor 62 is greater than 50V.
The next step in the example sequence shown in
At this point a read signal may be applied to the gates of transistors 82a-82n such that a small current (˜several microamperes) is simultaneously pulled through each leg of anti-fuse block 30 (block 115). For example, the read signal coupled to the gates of transistors 82 may be fed from a current mirror to establish the small current flow through transistors 82 for purposes of reading the state of each anti fuse 32. In this configuration, the sources of each of the trimming MOSFETs 33 are essentially connected to ground through a high-impedance. In the event that a particular anti-fuse 32 is programmed, the potential at the source of the associated trimming MOSFET 33 floats up to the difference between the gate-to-source voltage (Vgs) and the threshold voltage (Vt) of the associated trimming MOSFET 33. In other words, the voltage at the source (Vs) of a particular MOSFET 33 associated with an anti-fuse element 32 that has been blown (programmed) is Vs=Vgs−Vt. On the other hand, if a particular anti-fuse 32 remains open (not programmed), then the source of the associated trimming MOSFET 33 is at or near ground potential.
After the read signal has been applied to anti-fuse block 30, the source voltage of each of trimming MOSFETs 33 may be latched (stored) in corresponding latch element 81 (block 116). In one embodiment, latching of the state of each anti-fuse programming element occur when the VDD pin (node 70) crosses 5V. Latch element 81 may comprise any one of a number of well-known latch circuits or devices, e.g., an ordinary Set/Reset (R/S) latch. After the source voltages of each MOSFET 33 have been latched in each of the corresponding latch elements 81, transistor 76 (N2) is turned off, thereby turning off transistor 78 (P1). Transistor 77 (N3) is also turned on. These later steps effectively turn off isolation unit 45, causing anti-fuse block 30 to be isolated from the voltage produced by tap transistor 41 at node 43, thereby transitioning the power IC device back to a normal mode of operation.
Although the present invention has been described in conjunction with specific embodiments, those of ordinary skill in the arts will appreciate that numerous modifications and alterations are well within the scope of the present invention. Accordingly, the specification and drawings are to be regarded in an illustrative rather than a restrictive sense.
| Number | Date | Country | |
|---|---|---|---|
| Parent | 13066624 | Apr 2011 | US |
| Child | 13933746 | US | |
| Parent | 12800054 | May 2010 | US |
| Child | 13066624 | US |
