This application claims priority under 37 CFR Section 1.55 to China Patent Application No. 201810626274.X, filed on Jun. 15, 2018, and titled “Method and Apparatus for Reducing Coupling Between Word Lines and Control Gate Lines in a Flash Memory System,” which is incorporated by reference herein.
A method and apparatus are disclosed for reducing the coupling that otherwise can arise between word lines and control gate lines in a flash memory system due to parasitic capacitance and parasitic resistance.
Digital non-volatile memories are well known. For example,
Table No. 1 depicts typical voltage ranges that can be applied to the terminals of memory cell 100 for performing read, erase, and program operations:
In the top row of cells shown in
In the second row of cells shown in
With reference to
The parasitic capacitance can be modeled with: (1) parasitic capacitor 210 located within each cell 100, with one terminal connected to a word line and one terminal connected to a control gate line, and (2) parasitic capacitor 220 located within each cell 100, with one terminal connected to a word line and one terminal connected to floating gate 103 within the cell.
The effect of parasitic capacitors 210 is that there is voltage coupling between adjacent word lines and control gate lines that responds to changes in voltage on the word lines and/or control gate lines. The effect of parasitic capacitors 220 is that there is voltage coupling between word lines and floating gates within each cell 100 that responds to changes in voltage on the word lines and/or floating gates.
Parasitic capacitors 210 and 220 will cause word lines and control gate lines to take longer to charge to a certain voltage and longer to discharge. This parasitic capacitance has the unwanted effect of varying the current through each cell 100 during a discharge, which can cause read errors. As a result, the margin of error for read sensing operations is reduced. The problem is exacerbated as the target switching speed of the word line and control gate lines increases.
In addition, each word line and control gate line will have a large parasitic resistance. This resistance is due to the relative small size of the devices and the line width. The parasitic resistance can be modeled with parasitic resistors 230 located between cells 100 in each row.
The additional ΔV on control gate line 202 causes an increase of cell current during the read operation. If the read operation does not provide sufficient time for control gate line 202 to discharge from VCG+ΔV to VCG, then a selected cell that is storing a “0” may be misinterpreted as containing a “1.” To avoid this problem, the switching speed must allow for a discharge period on the order of 10's of nanoseconds. Thus, parasitic capacitance and parasitic resistance will result in a less accurate system.
What is needed is a flash memory system that reduces the parasitic capacitance between word lines and control gate lines and between word lines and floating gates in a flash memory system.
A method and apparatus are disclosed for reducing the coupling that otherwise can arise between word lines and control gate lines in a flash memory system due to parasitic capacitance and parasitic resistance.
The effect of decoupling circuit 410 is depicted in
Another embodiment is shown in
In instances where the row of word line 201 and control gate 202 is not selected, word line 201 will be low. Switch 602 will be closed. The output of inverter 607 will be high, and switch 601 will be open. Switches 604 and 605 also will be closed, such that the voltage VCG−ΔV is provided to control gate line 202.
During a program operation, switches 603 and 604 will be closed, such that the voltage Vep(HV) will be provided to control gate line 202.
During an erase operation, switch 606 will be closed, such that control gate line 202 will be pulled to ground.
It should be noted that, as used herein, the terms “over” and “on” both inclusively include “directly on” (no intermediate materials, elements or space disposed therebetween) and “indirectly on” (intermediate materials, elements or space disposed therebetween). Likewise, the term “adjacent” includes “directly adjacent” (no intermediate materials, elements or space disposed therebetween) and “indirectly adjacent” (intermediate materials, elements or space disposed there between), “mounted to” includes “directly mounted to” (no intermediate materials, elements or space disposed there between) and “indirectly mounted to” (intermediate materials, elements or spaced disposed there between), and “electrically coupled” includes “directly electrically coupled to” (no intermediate materials or elements there between that electrically connect the elements together) and “indirectly electrically coupled to” (intermediate materials or elements there between that electrically connect the elements together). For example, forming an element “over a substrate” can include forming the element directly on the substrate with no intermediate materials/elements therebetween, as well as forming the element indirectly on the substrate with one or more intermediate materials/elements there between.
Number | Date | Country | Kind |
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2018 1 0626274 | Jun 2018 | CN | national |
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