Patent Application
20060031032
The invention relates generally to signal acquisition systems and, more particularly, to a method and apparatus for selecting optimal sampling points in a logic analyzer.
Signal acquisition devices such as logic analyzers (LAs) are instruments used for verifying and debugging digital circuits. A logic analyzer verifies that a digital circuit is working and provides information for troubleshooting such a circuit. The logic analyzer is capable of capturing and displaying many signals of the digital circuit at one time and analyzing their timing relationships. Since timing relationships in digital circuits are paramount to their correct functioning, determining optimal sampling points for capturing such information in a logic analyzer is necessary for proper troubleshooting and problem diagnosis. Optimal sampling points are determined by a relationship between desired signals and an externally supplied clock. If the time that a data sample is acquired by the logic analyzer (according to the external clock) does not coincide with a time that a signal under test (SUT) is stable, such a condition will introduce skewing effects (i.e., invalid data) in the resultant output. It is therefore important to conduct data valid window analysis (DVWA) to find the optimal data sampling point in the SUT relative to the external clock transition to obtain valid data.
The LA samples data at a very high resolution. This allows a user to visually inspect a channel's data in a waveform display and, with much effort, visually determine whether the channel's data is stable with respect to a clock transition. Visual determination requires a user to inspect adjacent data sample points for same values because two adjacent values that are the same (i.e., a logical 1 or 0) value indicate data stability. This operation may involve taking many LA data acquisitions or it may require inspection of many clock transitions within a single acquisition, depending on the nature of the channels and clocks being used. If data stability is not obtained, then the user must manually make incremental adjustments to the LA's sampling tsetup and thold parameters for a signal to sample data for correct DVW results. This is a tedious operation when many channels must be compared and adjusted.
One way to determine data stability on a channel is to see where the high resolution data is stable with respect to a clock edge. Another way to determine data stability is to run an LA trigger program that checks for data setup and hold violations within a specified range and then triggers if a violation is found. A trigger program is a set of directions to the LA acquisition hardware indicating actions to be taken when a data event of interest is detected. When the LA executes a trigger program during a data acquisition, the resulting set of acquisition samples satisifies the logic conditions of the program. In most cases, the trigger program directs the acquisitions to stop (or complete the filling up of a data buffer) when an event of interest (for example, a violation of a setup and hold parameter ranges) is detected. One drawback of having to use a trigger program is that it may require many iterations of setup and hold adjustments and data acquisitions before a DVW can be determined for one channel. The problem is multiplied when many channels have to be so evaluated.
Various deficiencies in the prior art are addressed by the present invention of a method and apparatus for deskewing sampled data. The method in one embodiment includes the steps of (a) acquiring data samples from a first location in a first channel according to a first set of data collection parameters, (b) performing a validity analysis of the collected data samples and (c) upon a trigger parameter reaching a predetermined value, halting the acquisition of new data samples from the first location, adjusting a value of one or more of the first set of parameters, acquiring data samples from a second location in the first channel. Subsequently, an interactive completion of data acquisition signal is sent that provides selection of optimal sampling points for all analyzed channels for further data collection. In one embodiment of the invention, the validity analysis is a Data Valid Window analysis. In another embodiment of the invention, the validity analysis is a setup/hold violation analysis. The step of adjusting a value of one or more of the first set of parameters further comprises adding a time ΔT to a setup variable and a hold variable.
The teachings of the present invention can be readily understood by considering the following detailed description in conjunction with the accompanying drawings, in which:
To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures.
The subject invention provides for improved circuitry and operational methods for reducing the skew effects introduced by SUTs when under observation by, for example, LAs. Generally speaking, the invention performs automatic searches for DVWs in an operational mode denoted as Data Valid Window Analysis (DVWA). The results of DVWA show regions of stability and instability relative to a clock edge for each channel analyzed. Upon DVWA completion, the invention automatically selects a suggested sampling point for each analyzed channel and lets a user optionally apply that sampling point to tsetup and thold for that channel in any of the LA's synchronous clocking modes. The sampling point is considered to be the approximate center of a small setup/hold window that represents what the LA considers to be the setup and hold conditions at its probe tip for a channel. The invention picks the setup/hold window containing the suggested sampling point and sets that channel's tsetup and thold values. The user has the flexibility of changing the suggested sampling point (e.g., he can move the suggested sampling point into another DVW if desired).
At step 306, three additional values are established for conducting the SUT analysis. In one embodiment of the subject invention, values for parameters tsetup and thold that signify the relationship of the time surrounding a clock signal in the logic analyzer are set at a first extreme of an analysis range. Additionally, a trigger program is set to a first state to monitor data acquisition activity by looking for setup and hold violations. Once these initial states and values are established, the method proceeds to step 308, where the process of acquiring data from a channel being analyzed is performed. The process of acquiring data is known to those skilled in the art and can be found, for example, in “The XYZs of Logic Analyzers”, Sep. 20, 2002 by Tektronix, Inc. of Beaverton, Oreg. An exemplary method of calculating DVWs may be found at “High Speed State-Analyzer Measurements Call For Precise Sample Positioning” by Sontag and Nygaard and “Debugging the wireless boundary shift” by Woodward and Herron, all of which are herein incorporated by reference in their entireties.
Once data is acquired at a given clock sample, the method proceeds to step 310 where a first decision process is performed. Specifically, this first process evaluates whether a trigger event has occurred during the data acquisition period. Trigger activation occurs by the detection of a set up/hold violation. If a trigger event (i.e., a setup/hold violation) has activated the trigger of first decision step 310, then the method proceeds to step 312 where information regarding an invalid data window is stored. In one embodiment of the invention, one data invalid bit for the analyzed channel is stored.
If a trigger event does not occur during the analysis, then the method proceeds from the first decision step 310 to a second decision step 311 where channel analysis halt conditions are determined. Specifically, at step 311 the method takes additional factors into consideration when analyzing channels that include one or more of the following: detecting a timeout condition, suspension of the analysis by a user “abort” command and determining if the number of data acquisition samples has exceeded a user-defined quality value (one of the initialization parameters defined in step 304). If any of the halt conditions occur, channel analysis is halted and the method proceeds to step 313 where information regarding a valid data window is stored. In one embodiment of the invention, one data valid bit for the analyzed channel is stored. If none of the halt conditions occur, the method loops back to step 308 where another data sample is acquired at a subsequent sample point.
In one embodiment of the invention discussed in detail below, bits that encode the results of valid and invalid data samples are stored as four 32-bit integers (for a total of 128 bits). Such integers are processed into a list of DVWs for each channel and ultimately sent to a user interface (explained in greater detail below) for display to the user.
Once DVW information is stored, the method proceeds to step 314 where a third decision step occurs. This third decision step 314 determines whether all data on a particular channel has been analyzed. If the answer to this query is negative, the method proceeds to step 316 where updated tsetup and thold values are determined. In one embodiment, new tsetup and thold values are determined by adding a time interval ΔT, where ΔT represents the time shift necessary to analyze the next set of samples away from the original tsetup and thold extremity values. In one embodiment, the original tsetup and thold values are at one extreme of the analysis range (i.e., a furthest point in the analysis range after a clock pulse) and the ΔT moves the sampled value temporally through the analysis range (i.e., to a furthest point in the analysis range prior to the clock pulse). Once the new tsetup and thold values are established, the method loops back to step 308 where data acquisition and DVW calculations are performed for the new samples until such time that another trigger event is activated as described earlier in step 310.
If all data on a particular channel has been analyzed, the query to third decision step 314 is answered positively and the method proceeds to step 318, where a fourth decision step is performed. Specifically, fourth decision step 318 inquires as to whether all channels that are desired to be analyzed have, in fact, been analyzed. If additional channels are to be analyzed, then the method proceeds to step 320 where the next channel to be analyzed is selected. Subsequently, the method loops back up to step 306 where tsetup and thold values and the trigger state are established for the new channel (i.e., at the furthest point in the analysis range after a clock pulse) and the acquisition and subsequent triggering evaluations are performed for the new channel until such time that trigger and data analysis events on that channel are completed in accordance with the steps described above.
If additional channels are not to be analyzed, the method proceeds to step 322 whereby an interactive completion signal is sent to a user. In one embodiment of the invention, the interactive completion signal allows the user to view the results of the DVW calculations and overall analysis and decide whether to accept (and subsequently readjust sample points in each of the DVWs) or whether to allow the analysis to continue with preselected data points. The method ends at step 324. Note that while the subject method has been discussed and presented as occurring in real-time, it is also possible to collect all data samples from all channels and store such information for processing and analyzing at a time decided upon by the user before collecting additional data based on the optional sampling points in each channel.
In key 408, the Invalid Data Area block may be black, the Data Valid Window block may be colored blue, the S/H Violation block may be colored magenta, the Suggested Sample Point block may be colored yellow, and the Current Sample Point block may be colored green. Corresponding areas in Screen Display 400 are displayed in corresponding colors. For example, all Data Valid Window areas 412 are displayed in blue, and all Suggested Sample Points 418 are displayed in yellow.
In this figure, eight channels have been analyzed (A2[0] through A2[7]) (depicted in first field 402) in a range between 8 ns before the clock edge 410 to 8 ns after clock edge 410. Each channel shows one or more DVWs and DIWs. The valid data areas are denoted as relatively thicker horizontal bars 412, and the invalid data areas are denoted as relatively thinner horizontal lines 414. For sake of clarity, only first channel A2[0] has been labeled with the DVW and DIW legends in the figure. In a center DVW for each channel 412C, a first diamond shaped marker 416 denotes the current setup and hold sample point for a channel. In this example, all current setup and hold sample points for all channels are defaulted to the same point so as to be in vertical alignment. A second diamond marker 418 near the current points 416 represents the suggested sample points selected by the subject method. These points are also represented as numbers in the “Suggested Sample Point” column to the right of the data in third field 404. A user may open a dialog by pressing the “Apply . . . ” button 420 and apply the suggested points to the analyzed channels for a desired synchronous clocking mode. As shown in
The method of the subject invention is implemented by passing commands and data through a series of software layers between a user and module acquisition hardware.
The setup information (identified as Module command information in solid line format 520 in the key) is sent through an AutoDeskew Service module 502, which acts as a shell to communicate with an AutoDeskew Manager module 504 for the selected instrument. The Service module 502 contains code to handle each of the different setups from the interface 400 as well as beginning the analysis and sending various exceptions to various error conditions. The AutoDeskew Manager module 504 manages the received setup information and coordinates DVWA activities. For example, the Manager module 504 keeps track of what kind of analysis is being performed, which channels are being analyzed, the analysis range, the clocking that will be used for analysis, and the analysis quality.
Upon starting analysis, the AutoDeskew Manager module 504 sends a command to the AutoDeskew Run Control module 506. The Run Control module 506 is responsible for responding to completion notifications for each phase of the analysis and then telling the AutoDeskew Manager module 504 to begin the analysis. The AutoDeskew Manager module 504 forwards the setup information and Start command to module hardware for each module that comprises the instrument by invoking the services of a LA Module Driver 508. In this example, a single instrument represented by LA Module hardware 516 is depicted although multiple instruments are within the scope of the application. The LA Module Driver 508 formulates the commands recognized by the LA module hardware 516.
All commands going to, and data results from, the LA module hardware 516 must go through a VISA API layer 510, which manages communications with all such modules on the system. The VISA API layer 510 must communicate with a Windows kernel driver 516 that manages operation of the VXI-PCI bridge, a piece of hardware that provides a path to connect the system VXIbus with a PCI bus containing the system LA modules. The kernel driver provides mechanisms for programming the LA module hardware 516, notifying the application when LA module data operations complete, and returning LA module data results to the LA application. A Windows kernel driver is a software module that controls an attached piece of electronic hardware. Such software can be found on any operating system (Windows and Linux are two examples), although each operating system has its own requirements on how a driver should be designed. A VXI-PCI bridge is a piece of electronic hardware that must provide data transfer and event notification between a PCI bus and a VXI bus, which are two well-known computing bus standards.
Finally, the AutoDeskew setup parameters (analysis type, channels, clocking, quality number, and analysis range) arrive at the LA module hardware 516. The LA module hardware 516 contains special firmware (programming) that implements the AutoDeskew analysis. The LA module hardware 516 is connected through probing (not shown) to a SUT 518 which is the circuit being probed. The LA module hardware 516 uses the setup information to configure itself for sampling data (identified as Results information in double solid line format 524 in the key) through the connected probes.
When the AutoDeskew analysis is completed, the LA module hardware 516 sends a message (identified as Notification information in dashed line format 522 in the key and in one embodiment is a “Notify Done” message) that propagates up through the PCI-VXI bridge kernel driver 514, the VISA API 510 and into a set of Message-handling modules 512. The set of Message-handling modules 512 routes notification messages to the AutoDeskew Run Control module 506. The Run Control module 506 routes the notification messages back to the AutoDeskew Manager module 504. The AutoDeskew Manager module 504 in turn sends a notification message to the AutoDeskew Service module 502, which then alerts the user interface 400 that new data is available. At this point, the user interface 400 queries the Service module 502 for the analysis results, which results in a new stream of commands down through all of the layers to the LA Module 516, and subsequently the results are formatted and passed back to the user interface 400, where they are displayed for the user.
An optional additional feature of the subject invention, a second analysis mode identified as setup/hold violation analysis (SHVA), allows the user to test regions of each channel for setup and hold violations, i.e., the user establishes an automated test to report the stability of specified regions that are alleged to be stable (no violations). For example, if the user applies the results of the most recent DVW analysis to a synchronous clocking setup to get optimal data sampling points, SHV analysis tests the extent of a region around each sampling point for its stability. Zero violations reported indicates stability.
As discussed earlier with respect to
The ranges over which Setup and Hold violation tests are performed are denoted by SHV range bars 606 that overlay the DVW 412 and DIW 414 areas (and correspond to the pairs of numbers in the columns to the right). Some SHV range bars 606 are entirely contained within a DVW (such as the bars for channels A2[0], A2[4], A2[5] and A2[7]). Accordingly, SHV analysis should produce no violations for those channels. For the other channels, the SHV range bars 606 are either overlapping into DIW areas 414 or entirely contained within a DIW (such as channel A2[2]). In those cases, violations will be produced from SHV analysis.
To set up for SHV analysis, the user must enter, through the user interface 400, which channels are to be analyzed, the clocking specification (manual or custom), the Setup/Hold violation window search range to be applied to all channels, and, optionally, the number of violations to look for. If the user does enter the optional violation count, then the SHV analysis proceeds until it finds that many violations and then stops. Otherwise, analysis proceeds until the user aborts the operation. Note that the user can manually adjust the Setup/Hold violation window search range for individual channels within the main data area 406.
The advantages of using SHVA instead of previously existing trigger programs are that the setting up of SHVA is easier than having the user set up a trigger program, in that he does not have to write the program. Additionally, the setup and hold violation ranges for each analyzed channel are visually tied to each channel's optimal data sampling point. The user does not have to flip back and forth between a module's clocking setup dialog and a trigger program's setup and hold violation definition dialog to make adjustments in each dialog. Further, the user can easily alternate between DVW and SHV analysis modes using incremental adjustments in the sampling points and setup and hold violation ranges until an optimal set of setup and hold violation ranges is found. These can then be applied and used for subsequent normal data acquisition trigger programs.
Accordingly, the subject method and apparatus automatically detect the optimal sampling points of an SUT to ultimately reduce skewing effects. While the foregoing is directed to the preferred embodiment of the present invention, other and further embodiments of the invention may be devised without departing from the basic scope thereof, and the scope thereof is determined by the claims that follow.
