Claims
- 1. A test apparatus for testing a first memory device, the first memory device having a plurality of memory cells each of which is structured to store a data bit, one data bit per memory cell, the test apparatus comprising:a processor having a processor bus; an input device coupled to the processor through the processor bus and structured to allow data to be entered into the test apparatus; an output device coupled to the processor through the processor bus and structured to allow data to be output from the test apparatus; a second memory device coupled to the processor through the processor bus, the second memory device structured to store a plurality of data bits; and a test circuit coupled to the processor, the test circuit comprising: a memory loader circuit coupled to the first memory device, the memory loader circuit structured to cause a plurality of data bits having a first logic level to be stored in the memory cells; a memory reader circuit coupled to the first memory device, the memory reader circuit structured to serially read a plurality of data bits from the memory cells after the memory loader circuit causes the plurality of data bits to be stored in the memory cells, and structured to output a plurality of the data bits read; and a comparator circuit coupled to the memory reader circuit to receive the plurality of data bits output, the comparator circuit structured to sequentially compare, for a predetermined duration of time, the plurality of data bits output with the first logic level.
- 2. The test apparatus of claim 1 wherein the comparator circuit compares the voltage level of the plurality of data bits output with a voltage level corresponding to the first logic level.
- 3. The test apparatus of claim 1 wherein the memory reader circuit comprises a circuit structured to read the data bits stored in all of the memory cells that were written to by the memory loader circuit.
- 4. The test apparatus of claim 1 wherein the memory reader circuit comprises a circuit structured to output all of the data bits read.
- 5. The test apparatus of claim 1 wherein the memory reader circuit further comprises a latch circuit structured to latch each of the data bits read by the circuit memory reader.
- 6. The test apparatus of claim 1 wherein the first logic level comprises a logic one.
- 7. The test apparatus of claim 1 wherein the first logic level comprises a logic zero.
- 8. The test apparatus of claim 1, further comprising a signal generator circuit structured to output a fail signal when the logic level of a data bit read by the memory reader circuit does not correspond to the first logic level.
- 9. The test apparatus of claim 1, further comprising a signal generator circuit structured to output a pass signal when the logic level of all of the data bits read corresponds to the first logic level.
- 10. A method for testing a memory device, the memory device having a plurality of memory cells for storing a plurality of data bits, the method comprising the steps of:conducting a plurality of device cycles to the memory device, each device cycle comprising: loading a data bit having a first logic level into a memory cell; and causing the memory device to output a data bit from a memory cell that was loaded; and conducting a single tester cycle for each of the plurality of device cycles, each tester cycle comprising detecting if the logic level of a plurality of the data bits output is the first logic level.
- 11. The method of claim 10 wherein the plurality of data bits for which the logic level is detected during a tester cycle comprises all of the data bits output from the memory device.
- 12. The method of claim 10, further comprising latching the data bit read between device cycles.
- 13. The method of claim 10 wherein the first logic level comprises a logic one.
- 14. The method of claim 10 wherein the first logic level comprises a logic zero.
- 15. The method of claim 10, further comprising generating a fail signal when the logic level of a data bit read does not correspond to the first logic level.
- 16. The method of claim 10, further comprising generating a pass signal when the logic level of all of the data bits read corresponds to the first logic level.
CROSS-REFERENCE TO RELATED APPLICATION
This application is a divisional of pending U.S. patent application Ser. No. 09/169,486, filed Oct. 9, 1998 now pending.
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