FIELD OF INVENTION
This invention pertains to computing systems. In particular, this invention pertains to the arithmetic logic unit of a Reduced Instruction Set Computer (RISC) which incorporates simultaneous execution of different operations of complex calculations.
BACKGROUND OF THE INVENTION
High speed processing systems can be achieved by using logic and fundamental arithmetic operations at a fast speed while reducing the complexity. The processing systems designed using RISC methodologies achieve high speeds by executing most of the instructions in one instruction cycle and at the same time reducing the circuitry required to manage instructions of different lengths. However, the time taken for executing different arithmetic operations can vary significantly in length of execution; for example, time taken to execute an arithmetic operation to increment is considerably less than time taken to execute an operation such as (A+B)/C*D. Thus, if both the above-described operations have to be performed in the same instruction cycle, the instruction cycle would be fairly large.
To overcome this limitation posed to the throughput of the processing system, it has been suggested to reduce the time taken to execute complex operations by portioning the complex operation into multiple operations and executing multiple operations in parallel. For example, the processor can execute both A+B and C*D operations at the same time and even determine if the value of the multiplication of C and D is equal to zero. In this scenario, where the product of C and D is used as a denominator in successive division, zero detection forms a critical timing path. If the processing system detects that the product of C and D will be a zero, then it can stop executing the operation rather than dividing with a zero.
SUMMARY OF THE INVENTION
The proposed invention performs the zero prediction at a much faster rate than the arithmetic operation itself, so that the Arithmetic logic unit can operate at a higher processing speed.
The zero detection circuit of the invention is useful in many cases such as, but not limited to, when the sum of two numbers is going to be used as denominator in the subsequent division or if the difference of A and B is used to multiply with another value C. Traditional arithmetic unit designs first perform the arithmetic function and then test the result for Zero. That requires a serial accumulation of execution throughput delay. Extremely high speed is achieved using the parallel prediction approach of performing the arithmetic operation and the Zero result prediction in parallel. One proposed system performs zero prediction in parallel to the addition, but fails to optimize the zero prediction process. This system performs the zero prediction by comparing one of the input with negative value of the other input. Even though zero prediction is performed in parallel, the zero prediction might take the same amount of time as the arithmetic operation and thus may not be able to halt the arithmetic operation. For example, if the zero is predicted earlier than the arithmetic operation, in certain situations it is more beneficial to halt the arithmetic operation to save time and power, rather than performing the arithmetic operation.
BRIEF DESCRIPTION OF THE FIGURES
FIG. 1 is a system level block diagram of a processor incorporating the invention.
FIG. 2 is a block diagram of the invention for use when two binary numbers are added.
FIG. 3 is a block diagram of the invention for use when binary numbers are decremented.
FIG. 4 is a block diagram of the invention for use when two binary numbers are subtracted.
FIG. 5
a is a block diagram of the 7 bit comparator block of the invention.
FIG. 5
b is a block diagram of the 7 bit inverter block of the invention.
FIG. 6 is a block diagram of the n bit Incrementer the invention. 10FIG. 7 is a block diagram of the n bit Negater of the invention.
FIG. 8 is a block diagram of the n bit Adder of the invention.
FIG. 9 is a flow chart of the method of the invention.
DETAILED DESCRIPTION OF THE FIGURES
FIG. 1 is a system level block diagram of a processor incorporating the invention. In FIG. 1, an arithmetic logic unit (ALU) 105 is shown according to one embodiment of the invention. The device comprises a controller 110, Zero predictor 115, and an arithmetic unit 120. The arithmetic logic unit 105 receives a control signal cntrl 125 and performs arithmetic operations on input X0-Xn 130 and Y0-Yn 135 and can generate multiple outputs which can be represented as Outputs Z0-Zn 140, and C 145. The controller 110, on receiving the control signal cntrl 125, determines the arithmetic operation that needs to be performed and activates both the arithmetic unit 120 and the zero predictor 115 using the activation signals cntrl_2150 and cntrl_3155, respectively. Zero predictor 115 will notify the controller 110 on determining if a zero is predicted or not using the control signal zero_sig 160. If a zero is predicted, then the controller 110 deactivates the arithmetic unit 120 using the control signal cntrl_2120. On the other hand, if a zero is not predicted, the arithmetic operation being performed by the arithmetic unit 120 is completed to generate the output.
FIG. 2 is a block diagram of the invention for use when two binary numbers are added. In this embodiment, zero predictor 115 predicts if the sum of two binary numbers, A0-An (2250-6, 2257-12 and 225n−6−n) and B0-Bn (2100-6, 2107-12 and 210n−6−n) is zero. Zero predictor 115 compares one of the binary numbers with the two's complement of the other binary number, if both values are the same a zero output is predicted, otherwise a zero is not predicted. As shown in FIG. 2, the zero predictor 115 comprises a series of 7 bit inverters (2051, 2052-205m) connected in parallel, series of 7 bit incrementers (2151, 2152-215m) connected in parallel and also a series of 7 bit comparators (2351, 2352-235m) connected in parallel to allow for faster computations. Zero predictor 115 computes the two's complement of one of the binary input (in this case shown in FIG. 2)—(B0-Bn) (2350-6, 2357-12 and 235n−6−n) is obtained by first obtaining the inverted value of binary input, INV(B0-Bn) (2300-6, 2307-12 and 230n−6−n) and incrementing the inverted value by using the series of 7 bit incrementers (2151, 2152-215m) connected in parallel. The first 7 bit incrementer 2151 accepts the 7 least significant bits of the inverted output INV(B0-B6) 2300-6 and carry input C0 2200 (the value of C0 is ‘1’) and generates the output—(B0-B6 ) 2400-6 and the carry bit C1 2201 and the process is further carried out until all the n bits of the—(B0-Bn) 2400−n are computed. The operation of the n-bit incrementer is explained in further detail in FIG. 6. Once the two's complement value—(B0-Bn) 2400−n is computed, the binary values of A0-An (2250-6, 2257-12 and 225n-6-n) and—(B0-Bn) (2400-6, 2407-12 and 240n−6−n) are compared using the series of 7-bit comparators (2351, 2352-235m, 235m+1) connected in parallel. The comparator output of each of the 7 bit comparators (2351, 2352-235m, 235m+1), Out0-6, Out7-12 and Outn−6−n (2450-6, 2457-12, 245n−6−n), and Outc 245c are all compared with zeros and if the values are equal to zero then zero is predicted, otherwise non zero value is predicted.
FIG. 3 is a block diagram of the invention for use when binary numbers are decremented. It is used where in the arithmetic operation that needs to be performed by the arithmetic logic unit is decrementing a binary input A0-An (2250-6, 2257-12 and 225n−6−n). In this embodiment, zero predictor 115 compares the value of the binary number, A0-An(2250-6, 2257-12 and 225n−6−n) and n-bit binary value of ‘1’ (3050-6, 3057-12 and 305n−6−n). If the input value is equal to ‘1’ a zero output is predicted, otherwise a zero is not predicted. As in the earlier case, the comparison is carried by a series of 7-bit comparators (2351, 2352-235m) connected in parallel and the outputs of the comparators Out0-6, Out7-12 and Outn−6−n (2450-6, 2457-12 and 245n−6−n) are compared with zeros and if the values are equal to zero then zero is predicted, otherwise non zero value is predicted.
FIG. 4 is a block diagram of the invention for use when two binary numbers are subtracted. This is used where in the arithmetic operation that needs to be performed by the arithmetic logic unit is subtraction on two binary inputs. In this embodiment, zero predictor 115 predicts if the difference of two binary numbers, A0-An(2250-6, 2257-12 and 225n−6−n) and B0-Bn (2100-6, 2107-12 and 210n−6−n) is zero. The binary values of A0-An (2250-6, 2257-12 and 225n−6−n) and B0-Bn) (2100-6, 2107-12 and 210n−6−n) are compared using the series of 7-bit comparators (2351, 2352-235m) connected in parallel. The comparator output of each of the 7 bit comparators (2351, 2352-235m), Out0-6, Out7-12 and Outn−6−n (2450-6, 2457-12 and 245n−6−n) are compared with zeros and if the values are equal to zero then zero is predicted, otherwise non-zero value is predicted.
FIG. 5
a is a block diagram of the 7 bit comparator block of the invention. In this embodiment of the 7 bit comparator 2351 the seven least significant bits (LSB) of the two binary numbers, A0-A6 (2250-6) and B0-B6 (2100-6) are compared. The 7 bit comparator 2351 compares the LSB input bits, A0 with B0, A1 with B1 through A6 with B6 respectively at the same time by using seven XOR gates in parallel. If the input bit A0 is equal to the input B0, then the output bit Out0 is equal to ‘0’, otherwise the output bit Out0 is equal to ‘1’.
FIG. 5
b is a block diagram of the 7 bit inverter block of the invention, and depicts an embodiment of the 7 bit inverter 2051 which inverts the logical value of the seven least significant bits (LSB) of the binary input, A0-A6 (2250-6). The 7 bit inverter 2051 inverts the logical state of the input bits, A0, A1 through A6 at the same time by using seven inverters connected in parallel. If the input bit A0 is at a logical state of ‘0’, then the output bit will be equal to ‘1’, otherwise the output bit will be a ‘0’.
FIG. 6 is a block diagram of the n bit Incrementer of the invention and illustrates an embodiment of the n-bit incrementer where the n bit input is incremented using a series of 7 bit incrementer blocks 2151, 2152 and 215n connected in parallel. The first 7 bit incrementer block consists of a 7 bit incrementer 6151 which receives the seven least significant bits (LSB) of the binary input A0-A6 (2250-6) and increments with the value of ‘1’ and generates the incremented output INC_Out0-6 (6100-6) and carry bit INC_Carry1 6151. The successive incrementer blocks 2152 through 215m comprises a 7 bit incrementer 6052, 605m, and a multiplexer MUX1 6201 through MUXm−1 620m−1 respectively. All the incrementer blocks (6051, 6052-605m) each receives 7 bits of the binary inputs A0-A6 (2250-6), A7-A12 (2257-12) and An−6-An (225(n−6)−n) respectively, and calculate the incremented output and carry output of the 7 bits simultaneously to generate INC_Out0-6 (6100-6), INC_Carry1 6151, INC_Out7-12 (6107-12), INC_Carry2 6152, INC_Out(n−6)−n (610(n−6)−n), and INC_Carrym−1 615m−1. The incrementer 6052,-605m increment the 7 bits of binary inputs A7-A12 (2257-12) and An−6-An (225(n−6)−n) assuming that the carry from the preceding block is a ‘1’. The 7 bit incrementers 6052 and 605m of the incrementer blocks generate the intermediate incremented outputs IND_Out7-12 (6257-12), IND_Carry2 6302, IND_Out(n'6)−n 625(n−6)−n), and IND_Carrym'1 630m−1 based on the assumption that the carry bit of the preceding adder block is a ‘1’, the multiplexers can't provide the output until the actual value of the carry bit is known. Thus, in the worst case situation, time taken to generate the output of n-bit incrementer is equal to the time taken by a 7 bit incrementer and time taken by the (m−1) multiplexers to identify and provide the output based on the carry bit of the incrementer block.
In another embodiment, the time taken by the n bit incrementer can be further reduced by predicting the value of carry bit of the preceding adder block. To predict the carry bit, the least significant bits (LSB) of the binary input of each incrementer block is verified, if the LSB is equal to ‘0’ then the carry bit will be a zero, and the multiplexer of the successive adder block can provide the output without waiting for the preceding adder block to generate the carry bit. For example, if the binary input A0 (2250) of the incrementer block 2151 is a zero, the incrementer block 2152 can provide the output at the same time as the incrementer block 2151. Thus, if all of the LSB input of all of the incrementer blocks are zero, the time taken to generate the output of the n-bit incrementer can be reduced significantly to the time taken to generate the output of a 7-bit incrementer. In another embodiment, the seven bit incrementer used in the circuit can be designed using a minimal number of gates (using the Quine-Mccluskey algorithm the number of gates can be reduced significantly) and thus generating the incrementer output with a maximum of three gate delay.
FIG. 7 is a block diagram of the n bit Negater of the invention and illustrates an embodiment of the n-bit negater that can be utilized to obtain a two's complement of the n bit binary input. The n-bit input is first inverted using a series of 7 bit inverter blocks (2051, 2052-205m) connected in parallel and then incremented by a binary value of ‘1’ by a series of 7 bit incrementer blocks (2151, 2152-215m) connected in parallel. A series of 7 bit inverter blocks (2051, 2052-205m) inverts the binary input A0-A6 (2250-6), A7-A12 (2257-12) and A1-An (225(n−6)−n) to generate INV(A0-A6) 7050-6, INV(A7-A12) 7057-12 and INV(An−6-An) 705(n−6)−n. The first 7 bit incrementer block consists of a 7 bit incrementer 6151 which receives the seven least significant bits (LSB) of the binary input A0-A6 (2250-6) and increments with the value of ‘1’ and generates the incremented output Neg_Out0-6 (7100-6) and carry bit Neg_Carry1 7151. The successive incrementer blocks 2152 through 215m comprises a 7 bit incrementer 6052, 605m, and a multiplexer MUX1 6201 through MUXm−1 620m'1 respectively. All the incrementer blocks (6051, 6052-605m) each receives a 7 bits of the inverted binary inputs INV(A0-A6) 7050-6, INV(A7-A12) 7057-12 and INV(An−6-An) 705(n−6)−n respectively, and calculate the incremented output and carry output of the 7 bits simultaneously to generate Neg_Out0-6 (7100-6), Neg_Carry1 7151, Neg_Out7-12 (7107-12), Neg_Carry2 7152, Neg_Out(n−6)−n 710(n−6)−n, and Neg_Carrym 715m. The incrementers 6052,-605m increment the 7 bits of the inverted binary inputs INV(A7-A12) 7057-12 and INV(An−6-An) 705(n−6 )−n assuming that the carry from the preceding block is a ‘1’. The 7 bit incrementers 6052 and 605m of the incrementer blocks generate the intermediate values of incremented outputs and carry outputs ND_Out1(7207-12), and carry ND_carry1 (7251) through ND_Outm(720(n−6)−n), and carry ND_carrym−1 (725m−1) based on their own assumptions of the carry bit of the preceding adder blocks, the multiplexers can't provide the output until the actual value of the carry bit is known. Thus, in the worst case situation, time taken to generate the output of the n-bit incrementer is equal to the sum of time taken by a 7 bit inverter block, time taken by a 7 bit inverter block and time taken by the (m−1) multiplexers to identify and provide the output based on the carry bit of the incrementer block.
In another embodiment, the time taken by the n bit negater can be further reduced by predicting the value of carry bit of the preceding adder block. To predict the carry bit, the least significant bits (LSB) of the binary input of each incrementer block is verified, if the LSB is equal to ‘0’ then the carry bit will be a zero, and the multiplexer of the successive adder block can provide the output without waiting for the preceding adder block to generate the carry bit. For example, if the value of the inverted binary input A0 (7050) of the incrementer block 2151 is a zero, the incrementer block 2152 can provide the output at the same time as the incrementer block 2151. Thus, if all of the LSB input of all of the incrementer blocks are zero then the time taken to generate the output of the n-bit negater can be reduced significantly to the sum of the time taken to generate the output of a 7-bit inverter and time taken to generate the output of a 7-bit incrementer.
FIG. 8 is a block diagram of the n bit Adder of the invention that illustrates an embodiment of the n-bit adder that generates the sum of two binary inputs A0-A6 (2250-6), A7-A12 (2257-12) and An−6-An (225(n−6)−n) and B0-B6 (2100-6), B7-B12 (2107-12) and B0-Bn (210(n−6)−n). The n-bit adder comprises a series of 7 bit adder blocks (8051, 8052-805m) connected in parallel. The adder blocks 8052-805m further comprises two 7 bit adders 80521, 80522 and 805m1, 805m2 and a multiplexer MUX1 8251 through MUXm 825m−1 respectively. The adder blocks 80521,-805m1 add the binary inputs assuming that the carry from the preceding block is a ‘1’ and the adder blocks 80522,-805m2 add the binary inputs assuming that the carry from the preceding block is a ‘0’. All the adder blocks (8051, 8052-805m) each receives 7 bits of the binary inputs A0-A6 (2250-6), A7-A12 (2257-12) and An−6-An 225(n−6)−n respectively, and calculate the sum of the 7 bits simultaneously to generate Add_Out0-6 8100-6, Add_Carry1 8151, Add_Out7-12 8107-12. Add_Carry28152, Add_Outn−6−n810(n−6)−n, and Add_Carrym−1 815m. The adders 80521, 80522 and 805m1, 805m2 in the adder blocks generate the intermediate sums and carry bits based, I1—Out7-12 82521, I1—Carry1 83011, I2—Out7-12 82521, I2—Carry1 83012, I1—Out(n−6)−n 825m1, I1—Carrym−1 830m1, I2—Out(n−6)−n 825m2, I2—Carry1 830m2,. on their own assumptions of the carry bit of the preceding adder blocks, the multiplexers can't provide the output until the actual value of the carry bit is known. Thus, in the worst case situation, time taken to generate the output of n-bit adder is equal to the time taken by a 7 bit adder and time taken by the (m−1) multiplexers to identify and provide the output based on the carry bit of the preceding adder block.
In another embodiment, the time taken by the n bit adder can be reduced by predicting the value of the carry bit of the preceding adder block. To predict the carry bit, the most significant bits (MSB) of both the binary inputs of each adder block are verified, if both the MSB are equal to ‘0’ then the carry bit will be a zero, and the multiplexer of the successive adder block can provide the output without waiting for the preceding adder block to generate the carry bit. For example, if both binary inputs A6 (2256) and B6 (2256) of the adder block 8051 are zeros, the adder block 8052 can provide the output at the same time as the adder block 8051. Thus, if all of the MSB inputs of all of the adder blocks are zero then the time taken to generate the output of the n-bit adder can be reduced significantly to the time taken to generate the output of a 7-bit adder. In one embodiment, the n-bit incrementer, n-bit negater and the n-bit adder can be implemented both for computing the arithmetic operations in both the zero predictor and the arithmetic unit.
FIG. 9 is a flow chart of the method of the invention. The method is accomplished in operation of the controller 110 of the arithmetic logic unit 105. The controller 110 operates in the idle state on receiving power (step 905). The controller 110 verifies if it received a control signal to initiate the arithmetic operation (step 910), and if the control signal is not received, the controller returns to the idle state, otherwise the controller 110 determines which arithmetic operation needs to the performed. If the controller 110 determines that the difference of two binary numbers need to be calculated (step 920), it activates the zero predictor 110 and the arithmetic unit to perform subtraction using the control signals cntrl_1155 and cntrl_2150 respectively (step 925 and step 930). The zero predictor determines if the difference of the two binary inputs will result in a zero output or not by using the zero signal 160. Then controller 110 verifies to determine if the zero output is predicted (step 935), controller 110 then commands the arithmetic unit to halt the subtraction (step 940) and returns to idle state, otherwise, the arithmetic unit completes calculating the difference of two inputs and returns to idle state.
If the controller 110 determines that the sum of two binary numbers need to be calculated instead of the difference (step 945), it activates the zero predictor 110 and the arithmetic unit to perform addition using the control signals cntrl_1155 and cntrl_2150 respectively (step 950 and step 955). The zero predictor determines if the sum of the two binary inputs will result in a zero output or not by using the zero signal 160. Then controller 110 verifies to determine if the zero output is predicted (step 960), controller 110 then commands the arithmetic unit to halt the addition (step 965) and returns to idle state, otherwise, the arithmetic unit completes calculating the sum of two inputs and returns to idle state. If the controller 110 determines that a binary number need to be incremented instead of the calculating the sum or difference (step 970), it activates the zero predictor 110 and the arithmetic unit to increment the binary input using the control signals cntrl_1155 and cntrl_2150 respectively (step 975 and step 980). The zero predictor 115 will then notify the controller 110 whether incrementing the binary input will result in a zero output or not using the zero signal 160. The controller 110 verifies to determine if the zero output is predicted (step 985), then it commands the arithmetic unit to halt the arithmetic operation (step 990) and returns to idle state, otherwise, the arithmetic unit completes the arithmetic operation and returns to idle state.
While a specific multicore method for an eight point FFT computation has been discussed herein, it will be apparent to those familiar with the art that the same method can be extended to transform input data (time domain data) comprising more than eight points. The method is not limited to implementation on one multiple core processor array chip, and with appropriate circuit and software changes, it may be extended to utilize, for example, a multiplicity of processor arrays. It is expected that there will be a great many applications for this method which have not yet been envisioned. Indeed, it is one of the advantages of the present invention that the inventive method may be adapted to a great variety of uses.
The multicore method discussed above is only one example of available embodiments of the present invention. Those skilled in the art will readily observe that numerous other modifications and alterations may be made without departing from the spirit and scope of the invention. Accordingly, the disclosure herein is not intended as limiting and the appended claims are to be interpreted as encompassing the entire scope of the invention.
INDUSTRIAL APPLICABILITY
The inventive zero predictor 115, arithmetic unit 120, controller 110, instruction set and method of FIG. 9 are intended to be widely used in a great variety of computer applications. It is expected that they will be particularly useful in applications where significant computing power and speed is required.
As discussed previously herein, the applicability of the present invention is such that the inputting information and instructions are greatly enhanced, both in speed and versatility. Also, communications between a computer array and other devices are enhanced according to the described method and means. Since the inventive zero predictor 115, arithmetic unit 120, controller 110, instruction set and method of FIG. 9 of the present invention may be readily produced and integrated with existing tasks, input/output devices and the like, and since the advantages as described herein are provided, it is expected that they will be readily accepted in the industry. For these and other reasons, it is expected that the utility and industrial applicability of the invention will be both significant in scope and long-lasting in duration.
Patent Application
20090292757
