Claims
- 1. A method of testing a system board having an area of interest, comprising:removing a cover to provide access to the area of interest on said system board; positioning a pattern plate having a plurality of guide holes therethrough relative to the area of interest, said pattern plate comprised of an insulating material; inserting through a desired said guide hole of said pattern plate a singnal probe to provide an electrical connection with a first signal at the area of interest; inserting through another desired said guide hole of said pattern plate a ground probe to provide an electrical connection with a ground at the area of interest, said ground probe being electrically coupled with said signal probe to provide a return ground path; connecting said probe to an external device for testing of said first signal; and replacing said cover to prohibit access to the area of interest on said system board after testing is completed.
Parent Case Info
This application is a divisional of U.S. patent applicantion Ser. No. 09/527,577 filed Mar. 16, 2000, now U.S. Pat. No. 6,429,644 issued Aug. 6, 2002, which was a divisional of U.S. patent application Ser. No. 09/143,228, filed Aug. 28, 1998, now U.S. Pat. No. 6,433,562 issued Aug. 13, 2002, entitled “Method and Apparatus of Interconnecting with a System Board”, the entirety of which is hereby incorporated by reference.
US Referenced Citations (12)
Non-Patent Literature Citations (1)
Entry |
“Auto-Test CPU Interface”, T. H. Davis and C. M. Renuart; IBM Technical Disclosure Bulletin, vol. 13, No. 11, Apr. 1971; pp. 3583-3584. |