Patent Application
20070020778
This invention generally relates to metrology methods in micro-integrated circuit manufacturing, and more particularly to an improved metrology method and process control monitoring (PCM) structure for determining and locating electrical continuity defects in integrated circuitry in an integrated circuit manufacturing process.
Since the introduction of semiconductor devices, the size of semiconductor devices has been continuously shrinking, resulting in smaller semiconductor chip size and increased device density. One of the difficult factors in the continuing evolution toward smaller device size and higher density has been the ability to consistently form reliable integrated circuit wiring at smaller critical dimensions. For example, the reliability and electrical continuity of integrated circuitry wiring is determined by electrical continuity measurement methods following a manufacturing step, referred to as acceptance testing (WAT), to quickly determine and correct processing variables that may be causing circuitry defects.
Frequently, in order to determine processing variable that may lead to electrical continuity defects, it is desirable to form a test circuitry portion on a portion of the process wafer, referred to as a process control monitor (PCM), to determine the presence of defective circuitry portions. For example, the electrical integrity (continuity) of integrated circuitry is typically determined by passing an electrical signal through the process monitor control (PCM) circuitry.
One problem with prior art methods of electrical continuity WAT of PCM structures is that an uppermost metallization layer including a 2-dimensional circuit pattern is relied on for detecting circuitry defects in the most recently formed (uppermost) metallization layer. Frequently, testing of the most recently formed metallization layer is unable to detect the presence of defects in underlying metallization layers caused by formation of the most recently formed metallization layer.
For example, prior art metal continuity testing processes presently use 2-dimensional “snake shaped” metal line structures in testing of circuitry integrity in a metallization layer. If a circuitry defect is suspected in underlying metallization layers, frequently, the overlying layers must be removed to locate the defective area.
There is therefore a need in the semiconductor manufacturing art to develop an improved metrology method and integrated circuit monitoring structure to improve the identification and location of integrated circuit electrical continuity defects.
It is therefore an object of the invention to provide an improved metrology method and integrated circuit monitoring structure to improve the identification and location of integrated circuit electrical continuity defects, while overcoming other shortcomings of the prior art.
To achieve the foregoing and other objects, and in accordance with the purposes of the present invention, as embodied and broadly described herein, the present invention provides a 3-dimensional PCM structure and method for using the same for carrying out 3-dimensional integrated circuit wiring electrical testing and failure analysis in an integrated circuit manufacturing process.
IN a first embodiment, the method includes forming a first metallization layer; carrying out a first wafer acceptance testing (WAT) process to test the electrical continuity of the first metallization layer; forming first metal vias on the first metallization layer conductive portions and a second metallization layer comprising metal islands on the first metal vias wherein the metal islands electrically communicate with the first metallization layer to form a process control monitor (PCM) structure; and, carrying out a second WAT process to test the electrical continuity of the first metallization layer.
These and other embodiments, aspects and features of the invention will be better understood from a detailed description of the preferred embodiments of the invention which are further described below in conjunction with the accompanying Figures.
Although the method and apparatus of the present invention is explained and is particularly advantageous for determining the existence of and location of defects in copper or copper alloy metallization layers forming portions of a process control monitor for determining the reliability of an integrated circuit manufacturing process, it will be appreciated that other conductive materials including aluminum and tungsten may be used. Further although, the nature of underlying metallization layer metal interconnect defects are discussed with respect to via induced metal island corrosion (VIMIC) effects, it will be appreciated that the 3-dimentional metal interconnect process control monitor (PCM) structure including a method for detecting and locating metal interconnect defects may be applied, in general, to the detection and location of electrical continuity defects in underlying metallization layers.
Referring to
A first conventional electrical continuity parametric test, also referred to as electrical continuity wafer acceptance testing (WAT), is then undertaken to determine (test) the electrical continuity of metallization layer M1. For example, conventional automated electrical testing probe systems are used to probe the PCM structure for electrical continuity defects, e.g., by applying and detecting currents or Voltages through contact pads in communication with the first metallization layer, including a PCM interconnect line portion e.g., 12 forming a lengthened conductive line in snaked pattern on the surface of the metallization layer M1. For example, a 4-point or 2-point resistance measurements using conductive test pads in communication with the snaked line pattern may be used.
Following electrical continuity WAT of M1 metallization layer, in an important aspect of the present invention, an overlying metallization layer M2 is formed including via interconnect layer portions e.g., V1 which includes via portions e.g., 14A, 14B in electrical communication with upper metal island portions 16A and 16B. It will be appreciated that via interconnects, e.g., layer portion V1, and metallization layer M2, may be formed separately or by a dual damascene process in respective single or separate overlying dielectric insulating layers to form via portions e.g., 14A, 14B and metal island portions e.g., 16A and 16B.
Following planarization, e.g., chemical mechanical polishing (CMP) of the second metallization layer M2, a second WAT test is carried out to test for electrical continuity. In an important aspect of the invention, by adding the second metallization layer M2 including interlevel via portions to create a 3-dimensional interconnect layer layout for the PCM monitor, a second WAT test may now be undertaken and compared to the first WAT test according to the present invention, to detect via induced metal island corrosion (VIMIC) defects caused in metallization layer M1 by the formation process of metallization layer M2, for example VIMIC caused by formation of overlying via portions e.g., 14A and 14B.
For example, where the first WAT test is normal, e.g., detecting the absence of electrical opens in metallization layer M1, but where an abnormality is detected in the second WAT test after M2 formation (e.g., abnormally high electrical resistance), the result of the first WAT test is convoluted with, e.g., subtracted from, the second WAT test to verify the existence of the abnormality including providing information on a likely defect location.
Referring to
It will be appreciated that the relative widths and lengths of interconnect lines 12 and metal island portions e.g., 16A and 16B (including underlying via portions) may vary. For example, the M1 interconnect line 12 linewidth may be relatively wider or narrower, more preferably about the same width or wider with respect to metal island portions line widths e.g., 16A and 16B. In addition, the metal island portion lengths may be formed with a predetermined length and density e.g., where the spacing between metal island portions e.g., 16A and 16B may be varied depending on the desired PCM structure to test for the VIMIC effect. For example, advantageously, the VIMIC defects may be amplified by varying one or more of a relative density, line width, and line length of metal island portions e.g., 16A and 16B including underlying vias, in order to isolate a particular processing variable and enable easier identification of the VIMIC defect causing process variable.
Advantageously, by producing a 3-dimensional PCM interconnect layout structure including via portions in an uppermost metallization layer e.g., M2, the PCM structure can be used to determine electrical continuity failures in an underlying metallization layer, e.g., M1 following an overlying via and metallization layer formation process. For example, it has been found that overlying metallization layer formation processes including via formation can induce corrosion or erosion of underlying metallization layer portions, particularly when the respective metallization layer and vias are filled with copper. As noted above, such defects are also referred to as VIMIC defects. Although the precise mechanism of VIMIC defect formation is not understood, various processes including via etching, electro-chemical deposition (ECD), and chemical mechanical polish (CMP) processes are believed to contribute to such defects. The 3-dimension PCM structures of the present invention, advantageously allow the ability to detect such defects in underlying metallization layers without the necessity of removing the overlying metallization layers to expose the defective portion.
Referring to
For simplicity, only the metal islands and via portions are shown, but it will be appreciated that the metal island and via portions may be, and preferably are, formed as damascene structures in dielectric insulating layers. For example, shown in
In exemplary operation, a first WAT process for electrical continuity is carried out following a planarization, e.g., CMP process of metallization level e.g., M2A, M2B. Assuming a normal result, i.e., no electrical discontinuities, according to an aspect of the invention, an overlying metallization level e.g., M3A, M3B with associated via level e.g., V2A, V2B is formed and a second WAT process is carried out similar to the first WAT test. The second WAT results are then compared with, e.g., subtracted from the first second WAT test to determine the existence of an electrical discontinuity or defect e.g., VIMIC defect in metallization layer M2A.
Assuming an abnormal WAT results, e.g., an open circuit, a post failure analysis (PFA) process is then undertaken to more accurately determine the location and nature of the defect. For example, a charge inducing energy source, preferably an ion-beam source, is used to induce a Voltage and/or current in the PCM structure, also referred to as ion-beam induced Voltage Contrast (VC) imaging. The induced Voltage and/or current may then be amplified and imaged by known methods where the brightness level of the image corresponds to the level of Voltage and/or current in the PCM structure. For example, the location of a defective portion in the PCM structure in the post failure analysis (PFA) step is determined by locating an interface of contrasting levels of brightness in an image which corresponds to the location of an electrical discontinuity portion (e.g., VIMIC defect) in the PCM circuitry. Advantageously, current from underlying metallization layers is conducted to the upper surface to enable location and visualization of defects in underlying layers without requiring removal of overlying layers.
For example referring again to
Referring to
The preferred embodiments, aspects, and features of the invention having been described, it will be apparent to those skilled in the art that numerous variations, modifications, and substitutions may be made without departing from the spirit of the invention as disclosed and further claimed below.
