Resistors are critical components in applications such as analog, logic, and mixed signal integrated circuits. With continued scaling of device features and demands for higher processing speeds, integrated circuits consume more and more power and generate more heat. Joule heating, a process by which a current passing through a resistor releases heat has become a major concern for resistors. Often, the heat generated by a resistor will impact the resistor's neighboring devices (e.g., transistors, capacitors, etc.) and interconnects resulting in reliability and performance issues. This is especially problematic in the area of metallization where metal layers are sandwiched between insulating materials on a substrate.
Various solutions have been proposed to provide heat dissipation to integrated circuits. One such method is to attach heat sinks to the backside of a die or printed circuit board. Another is to blow air using cooling fans. However, such methods address the heat dissipation for the device package and, therefore, may not be particularly suitable or efficient in conducting heat away from neighboring devices or interconnects of a resistor.
Accordingly, what is needed is a method and structure for reducing the thermal impact on a resistor's neighboring devices and interconnects.
The features, aspects, and advantages of the disclosure will become more fully apparent from the following detailed description, appended claims, and accompanying drawings in which:
In the following description, numerous specific details are set forth to provide a thorough understanding of the embodiments of the present disclosure. However, one having an ordinary skill in the art will recognize that embodiments of the disclosure can be practiced without these specific details. In some instances, well-known structures and processes have not been described in detail to avoid unnecessarily obscuring the embodiments of the present disclosure.
Reference throughout this specification to “one embodiment” or “an embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present disclosure. Thus, the appearances of the phrases “in one embodiment” or “in an embodiment” in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. It should be appreciated that the following figures are not drawn to scale; rather, these figures are merely intended for illustration.
The resistor layer or resistor 40 is formed above the semiconductor substrate 20, and in one embodiment resistor 40 is formed above an isolation region such as a shallow trench isolation layer 30, as depicted in
A pair of metal terminals or terminal contacts 50 extend through an insulating layer (not shown) at opposite ends of resistor 40. The terminal contacts 50 connect resistor 40 to other components (not shown) in the integrated circuit. Each of the terminal contacts 50 is electrically connected through a plug or via 60 to a side of resistor 40. In an exemplary embodiment, the terminal contacts 50 are formed of metal, such as tungsten, copper, aluminum or other conductive material. The vias 60 are also formed of metal, such as tungsten, copper, aluminum or other conductive material. It is appreciated that the scope of the disclosure is not limited to any particular configuration or material of the terminal contacts 50 or the vias 60.
Disposed above and/or in close proximity with resistor 40 is the thermal protection structure 70. The thermal protection structure 70 comprises a metal cap layer 80 and a plurality of heat dissipating elements 90 in thermal conductive contact therewith. The metal cap layer 80 is formed of metal, such as tungsten, copper, aluminum or other conductive material; and as depicted in
The plurality of heat dissipating elements 90 may comprise a plurality of contact stacks 90, according to one embodiment of the present disclosure. As depicted in
The construction and structure of heat dissipating elements 90 should be substantially the same as the construction and structure of passive (e.g., metal layers) and/or active components of a device and may be formed at the same time that passive and/or active components are formed. To simplify fabrication of the plurality of heat dissipating elements 90, the same are made from the same or substantially same material as conventional interconnect structures, according to one exemplary embodiment.
It is understood by those skilled in the art that the placement and number of heat dissipating elements 90 (e.g., contact stacks and contact bars) disposed in semiconductor structure 10 as well as the dimensions of each of the heat dissipating elements 90 are determined based on the circuit pattern, the design rules for integrated circuit fabrication, and heat dissipation concerns for efficiently channeling the heat 100 from the resistor 40 to the substrate 20.
In operation, the thermal protection structure 70 provides a heat sink from the resistor 40 to the substrate 20, greatly reducing the temperature increase in an integrated circuit. The metal cap layer 80 receives the thermal flow or heat 100 generated from the resistor 40 and transfers the heat 100 to the heat dissipating elements 90, whereby the heat dissipating elements 90 dissipate the thermal energy 100 to and through the semiconductor substrate, away from neighboring devices and interconnects of the resistor 40. This arrangement spreads the thermal energy 100 across the thermal protection structure 70 so that it may be drawn off and dissipated to a larger surface area, such as substrate 20.
The resulting configurations and processes as taught herein are straightforward, economical, uncomplicated, highly versatile and effective, can be implemented by adapting known technologies, and are thus fully compatible with conventional manufacturing processes and technologies.
In the preceding detailed description, the present disclosure is described with reference to specific exemplary embodiments thereof. It will, however, be evident that various modifications, structures, processes, and changes may be made thereto without departing from the broader spirit and scope of the present disclosure. The specification and drawings are, accordingly, to be regarded as illustrative and not restrictive. It is understood that embodiments of the present disclosure are capable of using various other combinations and environments and are capable of changes or modifications within the scope of invention as expressed herein.
Number | Name | Date | Kind |
---|---|---|---|
5864169 | Shimura et al. | Jan 1999 | A |
20020063330 | Macris | May 2002 | A1 |
20030052386 | Yamaguchi | Mar 2003 | A1 |
20030116552 | Santoruvo et al. | Jun 2003 | A1 |
20030160298 | Nakamura | Aug 2003 | A1 |
20060231945 | Chinthakindi et al. | Oct 2006 | A1 |
20070108388 | Lane et al. | May 2007 | A1 |
20070120060 | Lane et al. | May 2007 | A1 |
20080102584 | Kerr et al. | May 2008 | A1 |
20090152679 | Harada | Jun 2009 | A1 |
20120049324 | Le Neel et al. | Mar 2012 | A1 |
Entry |
---|
Office Action dated Dec. 5, 2012 from corresponding application No. CN201010594455.2. |
Number | Date | Country | |
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20120002375 A1 | Jan 2012 | US |