METHOD AND STRUCTURE FOR LAYOUT AND ROUTING OF PCB

Abstract

Disclosed are a method and a structure for layout and routing of a PCB. The method includes: arranging signal lines, a power plane and a ground plane of the PCB in combination, where a portion of a reference plane for the signal lines is configured as a ground plane for providing a reference plane and return paths for the signal lines, to save routing spates. Layout of regions for the power supply, the ground and signal lines is appropriately designed, thereby improving the design density of a board, reducing the number of layers of the PCB, and saving cost.

Description

The application claims the priority to Chinese patent application No. 201710881052.8 titled “METHOD AND STRUCTURE FOR LAYOUT AND ROUTING OF PCB”, filed with the China National Intellectual Property Administration on Sep. 26, 2017, which is incorporated herein by reference in its entirety.

FIELD

The present disclosure relates to the technical field of layout and routing of signal lines and power supply lines of a PCB (printed circuit board), and in particular to a method and a structure for layout and routing of a PCB.

BACKGROUND

With the rapid development of the Internet and big data, and with the advent of the cloud computing era, cloud computing centers and big data centers have been rapidly developed and expanded, and the resulting requirement and usage of server and storage have increased. As the support for data processing and storage of the cloud computing and the big data, servers and storages directly determine the stability of the entire system.

As the core of the server, the design quality of the PCB directly determines the stability of the server. The PCB is mainly composed of signal lines and a power supply. In design, the design of the signal and the power supply should be comprehensively considered, and a high-quality PCB should be designed while minimizing the design cost.

A design solution of a conventional motherboard is a 12-layer board, where signal lines and power supplies on the stacked layers are designed from top to bottom as follows:

Layer Number	Function	Signal Line
L1	TOP	1 oz	PCIE DDR
L2	GND	1 oz	Ground
L3	Signal	1 oz	DDR, QPI, other lines
L4	Signal	1 oz	High-speed line, other lines
L5	GND	1 oz	Ground
L6	Power	2 oz	Power supply
L7	Power	2 oz	Power supply
L8	GND	1 oz	Ground
L9	Signal	1 oz	High-speed line, other lines
L10	Signal	1 oz	DDR, QPI, High-speed line
L11	GND	1 o	Ground
L12	BOT	1 oz	PCIE DDR

PCIE, DDR and high-speed lines are arranged on the TOP layer and the BOT layer, a complete ground plane is arranged on each of the L2, L5, L8, L11 layers, the high-speed lines and other lines are arranged on the L3, L4, L9 and L10 layers, power planes are arranged on the L6 and L7 layers. The signal lines on each layer of the above design have adjacent ground reference, and two layers of complete power planes and four layers of ground planes are provided, which is an optimal design method without considering cost.

According to the conventional design solutions, there is sufficient layout and routing space for power supplies, ground and signal lines, and there is also available space. In the current situation which is sensitive to costs of servers, servers are over-designed, which is unfavorable to enhancement of the competitiveness of the product.

SUMMARY

In view of the above issue, it is an object of the present disclosure to provide a PCB layout and routing method and a PCB layout and routing structure.

To achieve the above object, the following technology solutions are provided according to the present disclosure.

A method for layout and routing of a PCB is provided, which includes:

arranging signal lines, a power plane and a ground plane of the PCB in combination, wherein

a portion of a reference plane for the signal lines is configured as a ground plane for providing a reference plane and return paths for the signal lines, thereby saving routing spaces.

The method includes:

providing a PCB comprising 10 stacked layers, and

arranging a layout of signal lines and a power supply on each of the 10 stacked layers as:

Layer
Number	Function	Signal Line
L1	TOP	1 oz	PCIE, DDR
L2	GND	1 oz	Ground
L3	Signal	1 oz	DDR, High-speed line, other lines
L4	Power/GND	2 oz	Power supply, Ground
L5	Power/Signal	1 oz	QPI, Power supply
L6	Signal/GND/Power	1 oz	QPI, Ground, High-speed line,
			other lines
L7	Power/GND	2 oz	Power supply, Ground
L8	Signal	1 oz	DDR, High-speed line, other lines
L9	GND	1 oz	Ground
L10	BOT	1 oz	PCIE, DD

The layout of the PCB includes: a region for arranging PCH and PCIE slots, a region for arranging DIMM slots and CPU, and a region for QPI wiring, the region for QPI wiring is configured for connecting two CPUs, and the method includes:

configuring a region of the L4 layer corresponding to the region for QPI wiring and the region for arranging DIMM slots and CPU for a ground plane, and configuring a remaining region of the L4 layer for a power plane,

configuring a region of the L5 layer corresponds to the region for QPI wiring for arranging QPI signal lines, with the ground plane on the L4 layer being a reference plane corresponding to the QPI signal lines, and configuring a remaining region of the L5 layer for a power plane,

configuring a region of the L6 layer corresponding to the region for QPI wiring for arranging QPI signal lines, configuring a region of the L6 layer corresponding to region for arranging PCH and PCIE slots for arranging high-speed lines and other lines, and configuring a region of the L6 layer corresponding to the region for arranging DIMM slots and CPU for a ground plane, and

configuring a region of the L7 layer corresponding to the region of the L6 layer configured for arranging QPI signal lines and the region of the L6 layer configured for arranging high-speed lines and other lines for a ground plane, for providing reference for the QPI signal lines and the high-speed lines on the L6 layer, and configuring a remaining region of the L7 layer for power supply.

A structure for layout and routing of a PCB is provided, which includes: signal lines, a power plane and a ground plane, where a portion of a reference plane for signal lines is configured as a ground plane for providing a reference plane and return paths for the signal lines, thereby saving routing spaces.

The PCB includes 10 stacked layers, and a layout each of the 10 layers is:

Layer
Number	Function	Signal Line
L1	TOP	1 oz	PCIE, DDR
L2	GND	1 oz	Ground
L3	Signal	1 oz	DDR, High-speed line, other lines
L4	Power/GND	2 oz	Power supply, Ground
L5	Power/Signal	1 oz	QPI, Power supply
L6	Signal/GND/Power	1 oz	QPI, Ground, High-speed line,
			other lines
L7	Power/GND	2 oz	Power supply, Ground
L8	Signal	1 oz	DDR, High-speed line, other lines
L9	GND	1 oz	Ground
L10	BOT	1 oz	PCIE, DD

The layout of the PCB includes: a region for arranging PCH and PCIE slots, a region for arranging DIMM slots and CPU, and a region for QPI wiring (for connecting two CPUs), where,

a region of the L4 layer corresponding to the region for QPI wiring and the region for arranging DIMM slots and CPU is configured for a ground plane, and a remaining region of the L4 layer is configured for a power plane,

a region of the L5 layer corresponds to the region for QPI wiring is configured for arranging QPI signal lines, with the ground plane on the L4 layer being a reference plane corresponding to the QPI signal lines, and a remaining region of the L5 layer is configured for a power plane,

a region of the L6 layer corresponding to the region for QPI wiring is configured for arranging QPI signal lines, a region of the L6 layer corresponding to region for arranging PCH and PCIE slots is configured for arranging high-speed lines and other lines, and a region of the L6 layer corresponding to the region for arranging DIMM slots and CPU is configured for a ground plane, and

a region of the L7 layer corresponding to the region of the L6 layer configured for arranging QPI signal lines and the region of the L6 layer configured for arranging high-speed lines and other lines is configured for a ground plane, for providing reference for the QPI signal lines and the high-speed lines on the L6 layer, and a remaining region of the L7 layer is configured for power supply.

The present disclosure has the following beneficial effects.

The traditional layout where signal lines and power supplies are separately arranged on different layers is not adopted in the present disclosure. Instead, the signal lines, the power supplies and ground are arranged in combination, thereby improving the design density of the board. By appropriately designing the layout of regions of the power supply, ground and signal lines, the number of PCB layers can be reduced and costs can be saved.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic diagram showing a layout of a board;

FIG. 2 is a schematic diagram showing a layout of an L5 layer;

FIG. 3 is a schematic diagram showing a layout of an L4 layer;

FIG. 4 is a schematic diagram showing a layout of an L6 layer; and

FIG. 5 is a schematic diagram showing a layout of an L7 layer.

DETAILED DESCRIPTION

The present disclosure is described in detail in conjunction with the embodiments with reference to the drawings.

A method for layout and routing of a PCB includes the following steps 1) to 3).

In step 1), a shape of the PCB is determined and the main chips are arranged at appropriate positions on the PCB, including, as shown in FIG. 1, a region for arranging PCH (Platform Controller Hub) and PCIE (Peripheral Component Interconnect Express) slots, a region for arranging DIMM (dual-inline-memory-modules) slots and CPU (Central Processing Unit), and a region for QPI (Quick Path Interconnect) wiring, and the region for the QPI wiring is used for connecting two CPUs.

In step 2), a PCB including 10 stacked layers is provided, including L1 (TOP), L2, L3, L4, L5, L6, L7, L8 and L10 (BOT) from top to bottom.

In step 3), the L1 (TOP), L2, L3, L8, L9, L10 (BOT) layers are configured to have the conventional layout and routing, where:

the DDRs (double data rate) on the L3 layer and the DDR on the L8 layer are not changed, and the QPI signal lines are moved to the L5 layer and the L6 layer,

the high-speed lines and other lines in the conventional 12-layer structure is moved to the L3 layer and the L8 layer of the 10 layers,

a region of the L4 layer corresponding to the region for QPI wiring and the region for arranging DIMM slots and CPU is configured for a ground plane, and a remaining region of the L4 layer is configured for a power plane, as shown in FIG. 3,

a region of the L5 layer corresponds to the region for QPI wiring is configured for arranging QPI signal lines, with the ground plane on the L4 layer being a reference plane corresponding to the QPI signal lines, and a remaining region of the L5 layer is configured for a power plane, as shown in FIG. 2,

a region of the L6 layer corresponding to the region for QPI wiring is configured for arranging QPI signal lines, a region of the L6 layer corresponding to region for arranging PCH and PCIE slots is configured for arranging high-speed lines and other lines, and a region of the L6 layer corresponding to the region for arranging DIMM slots and CPU is configured for a ground plane, as shown in FIG. 4, and

a region of the L7 layer corresponding to the region of the L6 layer configured for arranging QPI signal lines and the region of the L6 layer configured for arranging high-speed lines and other lines is configured for a ground plane, for providing reference for the QPI signal lines and the high-speed lines on the L6 layer, and a remaining region of the L7 layer is configured for power supply, as shown in FIG. 5

The layout is as follows.

Layer
Number	Function	Signal Line
L1	TOP	1 oz	PCIE, DDR
L2	GND	1 oz	Ground
L3	Signal	1 oz	DDR, High-speed line, other lines
L4	Power/GND	2 oz	Power supply, Ground
L5	Power/Signal	1 oz	QPI, Power supply
L6	Signal/GND/Power	1 oz	QPI, Ground, High-speed line,
			other lines
L7	Power/GND	2 oz	Power supply, Ground
L8	Signal	1 oz	DDR, High-speed line, other lines
L9	GND	1 oz	Ground
L10	BOT	1 oz	PCIE, DD

The embodiments are only used to illustrate the present disclosure and are not intended to limit the present disclosure. Those skilled in the technical art can make some variations and improvements without departing from the spirit and scope of the present disclosure. All the equivalent technical solutions are also within the scope of the present disclosure, and the scope of the present disclosure should be defined by the claims.

Claims

1. A method for layout and routing of a PCB, comprising: arranging signal lines, a power plane and a ground plane of the PCB in combination, whereina portion of a reference plane for the signal lines is configured as a ground plane for providing a reference plane and return paths for the signal lines.

2. The method for layout and routing of a PCB according to claim 1, comprising: providing a PCB comprising 10 stacked layers, andarranging a layout of signal lines and a power supply on each of the 10 stacked layers as:

3. The method for layout and routing of a PCB according to claim 2, wherein the layout of the PCB comprises: a region for arranging PCH and PCIE slots, a region for arranging DIMM slots and CPU, and a region for QPI wiring, and the method comprises: configuring a region of the L4 layer corresponding to the region for QPI wiring and the region for arranging DIMM slots and CPU for a ground plane, and configuring a remaining region of the L4 layer for a power plane; andconfiguring a region of the L5 layer corresponds to the region for QPI wiring for arranging QPI signal lines, with the ground plane on the L4 layer being a reference plane corresponding to the QPI signal lines, and configuring a remaining region of the L5 layer for a power plane.

4. The method for layout and routing of a PCB according to claim 3, comprising: configuring a region of the L6 layer corresponding to the region for QPI wiring for arranging QPI signal lines, configuring a region of the L6 layer corresponding to region for arranging PCH and PCIE slots for arranging high-speed lines and other lines, and configuring a region of the L6 layer corresponding to the region for arranging DIMM slots and CPU for a ground plane; andconfiguring a region of the L7 layer corresponding to the region of the L6 layer configured for arranging QPI signal lines and the region of the L6 layer configured for arranging high-speed lines and other lines for a ground plane, for providing reference for the QPI signal lines and the high-speed lines on the L6 layer, and configuring a remaining region of the L7 layer for power supply.

5. A structure for layout and routing of a PCB, comprising: signal lines, a power plane and a ground plane, whereina portion of a reference plane for signal lines is configured as a ground plane for providing a reference plane and return paths for the signal lines.

6. The structure for layout and routing of a PCB according to claim 5, wherein the PCB comprising 10 stacked layers, anda layout each of the 10 layers is:

7. The structure for layout and routing of a PCB according to claim 6, wherein the layout of the PCB comprises: a region for arranging PCH and PCIE slots, a region for arranging DIMM slots and CPU, and a region for QPI wiring, wherein, a region of the L4 layer corresponding to the region for QPI wiring and the region for arranging DIMM slots and CPU is configured for a ground plane, and a remaining region of the L4 layer is configured for a power plane; anda region of the L5 layer corresponds to the region for QPI wiring is configured for arranging QPI signal lines, with the ground plane on the L4 layer being a reference plane corresponding to the QPI signal lines, and a remaining region of the L5 layer is configured for a power plane.

8. The structure for layout and routing of a PCB according to claim 7, wherein a region of the L6 layer corresponding to the region for QPI wiring is configured for arranging QPI signal lines, a region of the L6 layer corresponding to region for arranging PCH and PCIE slots is configured for arranging high-speed lines and other lines, and a region of the L6 layer corresponding to the region for arranging DIMM slots and CPU is configured for a ground plane; anda region of the L7 layer corresponding to the region of the L6 layer configured for arranging QPI signal lines and the region of the L6 layer configured for arranging high-speed lines and other lines is configured for a ground plane, for providing reference for the QPI signal lines and the high-speed lines on the L6 layer, and a remaining region of the L7 layer is configured for power supply.