The present invention is directed to integrated circuits and their processing for the manufacture of semiconductor devices. More particularly, the invention provides a method and resulting device for manufacturing a window structure for a tunnel dielectric in an EEPROM device using FLOTOX technology. But it would be recognized that the invention has a much broader range of applicability.
A variety of memory devices have been proposed or used in industry. An example of such a memory device is an erasable programmable read only memory (“EPROM”) device. The EPROM device is both readable and erasable, i.e., programmable. In particular, an EPROM is implemented using a floating gate field effect transistor, which has binary states. That is, a binary state is represented by the presence of absence of charge on the floating gate. The charge is generally sufficient to prevent conduction even when a normal high signal is applied to the gate of the EPROM transistor.
Numerous varieties of EPROMs are available. In the traditional and most basic form, EPROMs are programmed electrically and erased by exposure to ultraviolet light. These EPROMs are commonly referred to as ultraviolet erasable programmable read only memories (“UVEPROM”s). UVEPROMs can be programmed by running a high current between a drain and a source of the UVEPROM transistor while applying a positive potential to the gate. The positive potential on the gate attracts energetic (i.e., hot) electrons from the drain to source current, where the electrons jump or inject into the floating gate and become trapped on the floating gate.
Another form of EPROM is the electrically erasable programmable read only memory (“EEPROM” or “E2 PROM”). EEPROMs are often programmed and erased electrically by way of a phenomenon known as Fowler Nordheim tunneling. Still another form of EPROM is a “Flash EPROM,” which is programmed using hot electrons and erased using the Fowler Nordheim tunneling phenomenon. Flash EPROMs can be erased in a “flash” or bulk mode in which all cells in an array or a portion of an array can be erased simultaneously using Fowler Nordheim tunneling, and are commonly called “Flash cells” or “Flash devices.”
A limitation with the flash memory cell is processing techniques have been limited to further reduce cell size and increase device density. As merely an example, such memory cell often includes a specific size for a tunnel oxide window, which is used for conventional FLOTOX based EEPROM technologies. That is, the tunnel oxide window often cannot be reduced in size to less than 0.4 um, which limits the ability of further increasing device density. These and other limitations have been described in more detail throughout the present specification and more particularly below.
From the above it is seen that a memory cell structure that is easy to fabricate, cost effective, and dense is often desired.
According to the present invention, techniques for processing integrated circuits for the manufacture of semiconductor devices are provided. More particularly, the invention provides a method and resulting device for manufacturing a window structure for a tunnel dielectric in an EEPROM device using FLOTOX technology. But it would be recognized that the invention has a much broader range of applicability.
In a specific embodiment, the invention provides a method for forming an EEPROM integrated circuit structure. The method includes providing a substrate including a surface region, which is provided within a first cell region. The method includes forming a gate dielectric layer of first thickness overlying the surface of the substrate region. The method also includes patterning the gate dielectric layer to form a plurality of stripes. Each of the stripes is characterized by a second thickness, which is less than the first thickness. Each of the stripes has a predetermined width and a predetermined length that have been formed using a phase shift mask. At least one of the stripes includes a stripe portion traversing through a portion of the first cell region and other cell regions, which may have other devices. The method also includes forming a floating gate overlying a portion of the gate dielectric layer. The portion of the gate dielectric layer includes the strip portion traversing through the portion of the gate dielectric layer. The method includes forming an insulating layer overlying the floating gate and forming a control gate overlying the floating gate overlying the insulating layer and coupled to the floating gate. Preferably, the stripe portion traverses through the portion of the first cell region includes a tunnel window for a memory device.
In an alternative embodiment, the invention provides an EEPROM integrated circuit structure. The structure has a substrate that includes a surface region. Preferably, the surface region is provided within a first cell region. The structure also has a gate dielectric layer of first thickness overlying the surface of the substrate region and a select gate overlying a first portion of the gate dielectric layer. A floating gate is overlying a second portion of the gate dielectric layer and is coupled to the select gate. An insulating layer is overlying the floating gate. A control gate is overlying the insulating layer and is coupled to the floating gate. A tunnel window provided in a stripe configuration is formed within a portion of the gate dielectric layer. The portion of the gate dielectric layer is characterized by a second thickness, which is less than the first thickness.
Many benefits are achieved by way of the present invention over conventional techniques. For example, the present technique provides an easy to use process that relies upon conventional technology. In some embodiments, the method provides higher device yields in dies per wafer and improved device density. Additionally, the method provides a process that is compatible with conventional process technology without substantial modifications to conventional equipment and processes. Preferably, the invention provides for an improved tunnel oxide window, which leads to higher device densities. Depending upon the embodiment, one or more of these benefits may be achieved. These and other benefits will be described in more throughout the present specification and more particularly below.
Various additional objects, features and advantages of the present invention can be more fully appreciated with reference to the detailed description and accompanying drawings that follow.
According to the present invention, techniques for processing integrated circuits for the manufacture of semiconductor devices are provided. More particularly, the invention provides a method and resulting device for manufacturing a window structure for a tunnel dielectric in an EEPROM device using FLOTOX technology. But it would be recognized that the invention has a much broader range of applicability.
A method for fabricating an EEPROM device according to an embodiment of the present invention may be outlined as follows:
The above sequence of steps provides a method according to an embodiment of the present invention. As shown, the method uses a combination of steps including a way of forming a tunnel dielectric window for an EEPROM device. Other alternatives can also be provided where steps are added, one or more steps are removed, or one or more steps are provided in a different sequence without departing from the scope of the claims herein. Further details of the present method can be found throughout the present specification and more particularly below.
The method also includes forming a gate dielectric layer of first thickness overlying the surface of the substrate region. The gate dielectric layer is often a high quality thermal oxide, silicon oxynitride, or silicon nitride, depending upon the application. The method also includes patterning the gate dielectric layer to form a plurality of stripes. Each of the stripes is characterized by a second thickness, which is less than the first thickness. Each of the stripes has a predetermined width and a predetermined length that have been formed using a phase shift mask. Preferably, the pre determined width is less than 0.25 microns, which leads to a smaller cell size. At least one 407 of the stripes includes a stripe portion traversing through a portion of the first cell region and other cell regions, which may have other devices. Referring to
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It is also understood that the examples and embodiments described herein are for illustrative purposes only and that various modifications or changes in light thereof will be suggested to persons skilled in the art and are to be included within the spirit and purview of this application and scope of the appended claims.
Number | Date | Country | Kind |
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200310122971.5 | Dec 2003 | CN | national |