Patent Application
20150008566
Embodiments of the invention are related in general to the field of semiconductor devices and processes, and more specifically to the structure and fabrication method of panelized packaging for embedded semiconductore devices.
It is common practice to manufacture the active and passive components of semiconductor devices into round wafers sliced from elongated cylinder-shaped single crystals of semiconductor elements or compounds. The diameter of these solid state wafers may reach up to 12 inches. Individual devices are then typically singulated from the round wafers by sawing streets in x- and y-directions through the wafer in order to create rectangularly shaped discrete pieces from the wafers; commonly, these pieces are referred to as die or chips. Each chip includes at least one device coupled with respective metallic contact pads. Semiconductor devices include many large families of electronic components; examples are active devices such as diodes and transistors like field-effect transistors, passive devices such as resistors and capacitors, and integrated circuits with sometimes far more than a million active and passive components.
After singulation, one or more chips are attached to a discrete supporting substrate such as a metal leadframe or a rigid multi-level substrate laminated from a plurality of metallic and insulating layers. The conductive traces of the leadframes and substrates are then connected to the chip contact pads, typically using bonding wires or metal bumps such as solder balls. For reasons of protection against environmental and handling hazards, the assembled chips may be encapsulated in discrete robust packages, which frequently employ hardened polymeric compounds and are formed by techniques such as transfer molding. The assembly and packaging processes are usually performed either on an individual basis or in small groupings such as a strip of leadframe or a loading of a mold press.
In order to increase productivity by a quantum jump and reduce fabrication cost, technical efforts have recently been initiated to re-think certain assembly and packaging processes with the goal to increase the volume handled by each batch process step. These efforts are generally summarized under the title panelization. As an example, adaptive patterning methods have been described for fabricating panel-based package structures. Other technical efforts are directed to keep emerging problems such as panel warpage under control.
Applicants realized that successful methods and process flows for large-scale panels in the range from 16″×20″ to 21″×25″, as intended for semiconductor packaging, have to resolve key technical challenges. Among these challenges are achieving planarity of panels and avoiding warpage and mechanical instability, achieving low resistance connections and reaching high reliability backside chip connects, avoiding expensive laser process steps, especially through metal layers and epoxy layers, and improved thermal characteristics. For metallic seed layers, uniformity of the layers across the selected panel size should be achieved, yet electroless plating technology should be avoided. Further, the metallic seed layers nedd to strongly adhere to a variety of materials including silicon, metals, and insulators.
Applicants solved the challenges when they discovered process flows for packaged semiconductor devices which use adhesive tapes instead of epoxy chip attach procedures; and a sputtering methodology for replacing electroless plating; furthermore, the new process technology is free of the need to use lasers. As a result, the new process flows preserve clean chip contact pads and offer the opportunity to process both sides of a panel concurrently, greatly increasing productivity. In addition, the packaged devices offer improved reliability. A key contributor to the enhanced reliability is reduced thermo-mechanical stress achieved by laminating gaps with insulating fillers having high modulus and a glass transition temperature for a coefficient of thermal expansion approaching the coefficient of silicon.
Applicants adopted and modified a sputtering technology with plasma-cleaned an cooled panels, which produces uniform sputtered metal layers across a panel and thus avoids the need for electroless plating. Since the plasma-cleaning and sputtering procedure also serves to clean and roughen the substrate surface, the sputtered layers adhere equally well to dielectrics, silicon, and metals; they may be employed as connective traces, or may serve as seed layers for subsequent electro-plated metal layers.
Certain flows based on the modified processes may be applied to a plurality of discrete chips individually assembled on large panels; it is a technical advantage that other flows lend themselves to a plurality of whole semiconductor wafers before chip singulation. Many modified flows are applicable to any transistor or integrated circuit; other modified flows are particularly suitable forspecifically MOS field effect transistors (FETs), which have terminals on both chip sides. It is another technical advantage that some of the packaged devices offer flexibility with regard to the connection to external parts: they can be finished to be suitable as devices with land grid arrays, or as ball grid arrays, or as and QFN (Quad Flat No-Lead) terminals. Another family of packaged devices based on an inventive process flow offers dual purpose layer-to-layer interconnects that are also used as locating fiducials in the assembly process and may be operational on the front as well as on the back side of the packages.
In
At the sidewalls of chip 101 in device 100 in
It is preferred that the majority of the package surface, which does not serve as terminal areas, is protected by a rigid layer 160; a preferred choice is an insulator commonly called solder mask.
Another embodiment is a method for fabricating packaged semiconductor devices in panel format, shown in exemplary
In the next process step 291, the polymeric coat 210 is patterned in order to expose the terminal pads 202 of the devices. Thereafter, wafer 200 is diced along lines 285 into discrete chips 201. As shown in
In process step 292, an adhesive tape 221 is provided; preferably tape 221 is silicone-based. Then, a large metallic window frame 281 with a plurality of metal rims 280 is attached to the tacky surface of tape 221; a preferred metal of the frame is copper. Frame 281 defines the panel size; in this case, a large size of panel implies, for example, a format of 16″ by 20″, or larger; a panel of this size provides to the panel-format process flow a throughput volume 3.5 times the volume of an 8″ wafer. A batch process of this magnitude can improve productivity substantially. The frame includes a plurality of openings, or windows, framed by metallic rims 280 with sidewalls. The size 282 of an individual window is such that at least one chip 201 fits into the window, preferably a plurality of chips 201 aligned in an orderly array or grid. In the array, chips 201 are spaced from frame sidewalls 280a by gaps 231; similarly, adjacent chips are spaced by gaps from each other. The warpage of panel 281 is kept under control and minimized by the subsequent process steps and materials (see below).
In process step 293, semiconductor chips 201 are attached to tape 221 inside the windows of frame 281. Chips 201 are oriented so that chip terminals 202 face tape 221 and polymeric layer 210 is attached to tape 221. In this position, chip terminals 202 are protected from external influences and can thus conserve their original cleanliness. The perspective view of step 293 in
The process of step 294 in
Next, a carrier sheet 220 is placed over the assembly and attached to the planar surface 232 and 201b. The sheet, which is often referred to as a pre-preg film, is based on composite material including glass fiber impregnated with a gluey resin and selected for a CTE close to the CTE of silicon. Alternatively, for some device types the attachment of the carrier sheet is omitted.
In the next process step illustrated in step 295, panel 281 is turned over so that adhesive tape 221 faces up. Then, the adhesive tape 221 is removed, if necessary by raising the temperature. This action exposes the clean metallized terminal pads 202 of the chips surrounded by polymeric coat 210. Thereafter, panel 281 with its assembly is transferred to the vacuum and plasma chamber of an apparatus for sputtering metals.
During the processes summarized in step 296, the assembly of panel 281, with the exposed terminal pads, chip coats, and lamination surfaces, is plasma-cleaned. The plasma accomplishes, besides cleaning the surface from adsorbed films, especially water monolayers, some roughening of the surfaces; both effects enhance the adhesion of the sputtered metal layer. While the panel is being cooled, at least one layer 240a of metal is sputtered, at uniform energy and rate, onto the exposed chip and lamination surfaces across the panel. The sputtered layer adheres to the multiple surfaces by energized atoms that penetrate the top surface of the panel, creating a non-homogeneous layer between the surface material and sputtered layers.
Preferably, the step of sputtering includes the sputtering of a first layer of a metal selected from a group including titanium, tungsten, tantalum, zirconium, chromium, molybdenum, and alloys thereof, wherein the first layer is adhering to chip and lamination surfaces; and without delay sputtering at least one second layer of a metal selected from a group including copper, silver, gold, and alloys thereof, onto the first layer, wherein the second layer is adhering to the first layer. The sputtered layers have the uniformity, strong adhesion, and low resistivity needed to serve, after patterning, as conductive traces for rerouting; the sputtered layers may also serve as seed metal for plated thicker metal layers.
In optional step 297, at least one layer 240b of metal is electroplated onto the sputtered layers 240a. A preferred metal is copper. The plated layer is preferably thicker than the sputtered metal to lower the sheet resistance and thus the resistivity of the rerouting traces after patterning the plated and sputtered metal layers. Next, step 298 in
In addition, it is preferred to deposit and pattern rigid insulating material 260, such as so-called solder resist, to protect and strengthen remaining chip areas not used for extended contacts and between the rerouting traces. In order to apply to a large panel solder resist and other dielectric materials, photo-imagable materials, etchants, and others, a preferred recent technique uses an ultrasonic spray tool.
In the next process step, panel 281 is singulated into discrete devices; the preferred separating technique is sawing. The cuts may be made through laminated material 230 along lines 286 in
Another embodiment is an exemplary method for fabricating packaged semiconductor devices in panel format, illustrated in
In process step 390 of
In step 391, a compliant insulating material 330 is laminated, under vacuum suction, in order to cohesively fill any gaps 331 between the chips and to cover the chip surfaces and bumps 302. Preferably, the height 330a of the laminated material over the bump tops is between about 15 μm and 90 μm. The compliant material is selected to have a high modulus and a low CTE approaching the CTE of the semiconductor chips; it may be glass filled and may include liquid crystal polymers.
In the next process step, designated 392 in
During the processes summarized in step 393, the assembly of carrier 320, with the exposed metal bumps and lamination surfaces, is plasma-cleaned, while the panel is cooled, preferably below ambient temperature. The plasma accomplishes, besides cleaning the surface from adsorbed films, especially water monolayers, some roughening of the surfaces; both effects enhance the adhesion of the sputtered metal layer. Then, at uniform energy and rate, at least one layer 340a of metal is sputtered onto the exposed bump and lamination surfaces across the carrier. The sputtered layer is adhering to the surfaces.
Preferably, the step of sputtering includes the sputtering of a first layer of a metal selected from a group including titanium, tungsten, tantalum, zirconium, chromium, molybdenum, and alloys thereof, wherein the first layer is adhering to chip and lamination surfaces; and without delay sputtering at least one second layer of a metal selected from a group including copper, silver, gold, and alloys thereof, onto the first layer, wherein the second layer is adhering to the first layer. The sputtered layers have the uniformity, strong adhesion, and low resistivity needed to serve, after patterning, as conductive traces for rerouting; the sputtered layers may also serve as seed metal for plated thicker metal layers.
In optional step 394, at least one layer 340b of metal is electroplated onto the sputtered layers 340a. A preferred metal is copper. The plated layer is preferably thicker than the sputtered metal to lower the sheet resistance and thus the resistivity of the rerouting traces after patterning the plated and sputtered metal layers. The steps of patterning the sputtered and plated metal layers in order to create connecting traces between the bumps and enlarged package contact pads are preferably executed with a laser direct-imaging technology.
In addition, it is preferred, in step 395, to deposit and pattern rigid insulating material 360, such as so-called solder resist, to protect and strengthen remaining chip areas not used for extended contacts and between the rerouting traces. In order to apply solder resist and other dielectric materials, photo-imagable materials, etchants, and others, a preferred technique uses an ultrasonic spray tool. In the next process step 396, panel-size carrier 320 is singulated into discrete devices 370; the preferred separating technique is sawing. After singulation, respective parts 321 of carrier 320 remain with the finished packages of devices 370.
Another embodiment is a method for fabricating packaged semiconductor devices in panel format, illustrated in
In addition, whole semiconductor wafers 410 are provided, which incorporate a plurality of devices and circuits. The devices and circuits preferably have bondpads and terminals with metal bumps such as copper pillars (for example about 200 μm high).
In process step 491 (in
Next (step 492), the wafer surfaces on each panel side are uniformly coated with an insulating material 430, filling the gaps between the terminal bumps 411. The step of coating employs an ultrasonic spray apparatus suitable for uniformly spraying insulating materials selected from a group including polyimides, photo-image-able compounds, and dielectric spin-on compounds. Thereafter, panel 400, with wafers attached on both sides, is transferred to the vacuum and plasma chamber of a sputtering equipment.
During the processes summarized in step 493, panel 400 with the exposed metal bumps 411 and surfaces of coat 430, is plasma-cleaned. The plasma accomplishes, besides cleaning the surface from adsorbed films, especially water monolayers, some roughening of the surfaces; both effects enhance the adhesion of the sputtered metal layer. Then, at uniform energy and rate and while the panel is cooled from the back side, at least one layer 340a of metal is sputtered onto the exposed bump and coat surfaces on each panel side. The sputtered layer is adhering to the surfaces. As stated above in a previous method, the metal of the at least one sputtered layer is preferably a refractory metal; it is further preferred that a second sputtered layer, preferably including copper, is added onto the first layer without delay.
In step 494, the optional next processes of plating, patterning, and etching are performed in a manner analogous to the processes described above in a previous method. In addition, an optional deposition and patterning of a protecting solder resist layer is similar to previously described processes.
In step 495, the temperature is elevated to release adhesive layer 405 so that panel cores 401 and 402 can be separated. Thereafter in step 496, the wafers, supported by their respective panel cores, are individually diced. After the respective panel cores have been released by UV irradiation, discrete packaged semiconductor devices have been created. The devices have the technical advantage that the exposed back sides of the semiconductor chips can serve as excellent heat spreaders.
Another embodiment is an exemplary method for fabricating packaged semiconductor devices in panel format, illustrated in
In process step 590 of
In step 591, a compliant insulating material 530 is laminated, under vacuum suction, in order to cohesively fill any gaps 531 between the chips and to cover the protective coats 580. Preferably, the height 530a of the laminated material over the coat tops is between about 15 μm and 50 μm. The compliant material is selected to have a high modulus and a low CTE approaching the CTE of the semiconductor chips; it may be glass filled and may include liquid crystal polymers.
In the next process step, designated 592 in
In process step 593, the protective coat over the chip surface and terminals is removed, for instance by etching or in a water wash. This step exposes chip surface 501a and the chip terminals 502. Thereafter, carrier 520 is secured in a frame to restrain warpage and is transferred, with its assembled chips, to the vacuum and plasma chamber of an apparatus for sputtering metals.
During the processes summarized in step 594, the assembly of carrier 520, with the exposed chip terminals and lamination surfaces, is plasma-cleaned, while the panel is cooled, preferably below ambient temperature. Then, at uniform energy and rate, at least one layer 540a of metal is sputtered as seed metal onto the exposed chip terminals and lamination surfaces across all chips assembled on the carrier. The sputtered layer is adhering to the surfaces. As stated in more detail in a previous method, the step of sputtering preferably includes the sputtering of a first layer of a metal selected from refractory metals, followed without delay by the sputtering of at least one second layer of a metal, preferably copper. The sputtered layers have the uniformity, strong adhesion, and low resistivity needed to serve, after patterning, as conductive traces for rerouting; the sputtered layers may also serve as seed metal for plated thicker metal layers.
Further included in step 594 is the step of plating at least one layer 540b of metal onto the sputtered layers 540a. A preferred plated metal is copper. The plated layer is preferably thicker than the sputtered metal to lower the sheet resistance and thus the resistivity of the rerouting traces after patterning the plated and sputtered metal layers. The step of patterning the sputtered and plated metal layers is also included in step 594; the step creates connecting traces between the bumps and enlarged package contact pads and is preferably executed with a laser direct-imaging technology. The laser direct-imaging technology uses an out-alignment correcting technique.
In addition, it is preferred, in step 595, to deposit and pattern rigid insulating material 560, such as so-called solder resist, to protect and strengthen remaining chip areas not used for extended contacts and between the rerouting traces. In order to apply solder resist and other dielectric materials, photo-imagable materials, etchants, and others, a preferred technique uses an ultrasonic spray tool. In the next process step 596, panel-size carrier 520 is singulated into discrete devices 570; the preferred separating technique is sawing. After singulation, respective parts 521 of carrier 520 remain with the finished packages of devices 570.
Another embodiment is a method for fabricating packaged semiconductor devices in panel format, illustrated in
In process step 690, a metallic grid is provided which includes a plurality of metal rims 680 spaced by openings 682. Rims 680 are often referred to as fiducials; the sidewalls 680a of the fiducials are facing the openings 682. The preferred metal 681 of the rims is copper; one surface 683 of each rim has a solderable surface. One method for fabricating the grid is to provide a window frame of a sheet metal, which has one solderable surface, and then to form the array of openings by stamping or etching. In an alternative method, metal foils are laminated on both layers 603 and 604 of the second adhesive, with the respective solderable foil surfaces facing the adhesive layer. The metal foils are then patterned to create a plurality of fiducials to mark the openings 682 suitable for semiconductor chips. In step 690, a metallic grid is attached to at least one tachy side of carrier 600, as indicated by arrows 684 and 685, respectively; in exemplary
In process step 691, a plurality of semiconductor chips 610 is attached to the tacky layers on the surfaces of carrier 600 within the respective openings 682 between adjacent fiducials. Chips 610 are spaced from fiducials sidewalls 680a by gaps 612. The chips have a surface 610a with first terminals 611a facing the respective adhesive layer, and a second surface 610b with second terminals facing away from the respective adhesive layer. As an example, the chips may be power field effect transistors (FETs).
Several processes are summarized in step 692 of
Thereafter, panel 600, with wafers attached on both sides, is transferred to the vacuum and plasma chamber of a sputtering equipment. In step 693, both sides of panel 600 are plasma-cleaned. The plasma accomplishes, besides cleaning the surface from adsorbed films, especially water monolayers, some roughening of the surfaces; both effects enhance the adhesion of the sputtered metal layer. Then, at uniform energy and rate and while the panel is cooled from the back side, at least one layer 640a of metal is sputtered onto the exposed chip, fiducial, and lamination surfaces on each panel side. The sputtered layer is adhering to the surfaces. As stated above in a previous method, the metal of the at least one sputtered layer is preferably a refractory metal; it is further preferred that a second sputtered layer, preferably including copper, is added onto the first layer without delay.
In steps 694 and 695, the optional next processes of plating, patterning, etching, and photoresist removal of additional metal layers, such as copper, are performed in a manner analogous to the processes described above in a previous method. Furthermore, seed metal layers 640a are patterned. As a result of the patterning of plated and sputtered layers 641 and 640a, rerouting traces are created, which allow a redistribution of the second chip terminals from the second surface 610b to the surface 610a of the first terminals 611a.
After an optional encapsulation process between step 695 and step 696, the temperature is elevated to release layer 605 of the first adhesive so that panel cores 601 and 602 can be separated. Then, UV irradiation is initiated to release the layers 603 and 604 of the second adhesive and thus to separate the assembled strips of chips from the respective carriers. Thereafter in step 697, the device strips with their metallization-enhanced chips are individually diced. The devices have the technical advantage that the metallized back sides of the semiconductor chips can serve as excellent heat spreaders.
Another embodiment is a method for fabricating packaged semiconductor devices in panel format, illustrated in
In process step 790, a metallic grid is provided which includes a plurality of metal rims 780 spaced by openings 782. Rims 780 are often referred to as fiducials; the sidewalls 780a of the fiducials are facing the openings 782. The preferred metal 781 of the rims is copper; one surface 783 of each rim has a solderable surface. One method for fabricating the grid is to provide a window frame of a sheet metal, which has one solderable surface, and then to form the array of openings by stamping or etching. In an alternative method, a metal foil is laminated on layer 703 of the first adhesive, with the solderable foil surface facing the adhesive layer. The metal foil is then patterned to create a plurality of fiducials to mark the openings 782 suitable for semiconductor chips. In step 790, the metallic grid is attached to the tacky side of carrier 700a, as indicated by arrows 784.
In process step 791, a plurality of semiconductor chips 710 is attached to the tacky layer on the surface of carrier 700a within the respective openings 782 between adjacent fiducials. Chips 710 are spaced from fiducials sidewalls 780a by gaps 712. The chips have a surface 710a with terminals 711 facing the adhesive layer 703; for many chip types, their terminals have metal bumps.
Several processes are summarized in step 792 of
For step 793, a second panel, or carrier, 700b is provided, which has an insulating core 705. On both surfaces of core 705 is a tacky film, designated 706 and 707 in
Thereafter, in step 794 UV-irradiation is used on the first adhesives of both sides of the workpiece. Laminate carriers 700a and 700c are thus separated from the assemblies on both sides of the workpiece, and the surfaces of chips 710 and 715 with the terminals 711 and 716 (and their bumps), respectively, are exposed.
In step 795, the remainder of the workpiece with chips 710 and 715 attached on both sides, is transferred to the vacuum and plasma chamber of a sputtering equipment. In step 795, both sides of the workpiece are plasma-cleaned. The plasma accomplishes, besides cleaning the surface from adsorbed films, especially water monolayers, some roughening of the surfaces; both effects enhance the adhesion of the sputtered metal layer. Then, at uniform energy and rate and while the panel is cooled from the back side, at least one layer 740 and 741, respectively, of metal is sputtered onto the exposed chips, fiducial, and lamination surfaces on each panel side. The sputtered layer is adhering to the surfaces. As stated above in a previous method, the metal of the at least one sputtered layer is preferably a refractory metal; it is further preferred that a second sputtered layer, preferably including copper, is added onto the first layer without delay.
In step 796, the optional next processes of plating, patterning, etching, and photoresist removal of additional metal layers 742 and 743, such as copper, are performed in a manner analogous to the processes described above in a previous method. Furthermore, seed metal layers 740 and 741 are patterned. As a result of the patterning of plated and sputtered layers, rerouting traces are created; both sides of the workpiece have completed assemblies.
After an optional encapsulation process before step 797, the temperature is elevated to release layers 706 and 707 of the second adhesive so that the assemblies 770 and 771 on both sides of the second panel, or carrier, can be separated. Thereafter in step 798, the device strips with their metallization-enhanced chips are individually diced.
Another embodiment is a method for fabricating packaged semiconductor devices in panel format, illustrated in
In the next process step 891, second metal foils 810 and 811 are laminated to the first metal foils 804 and 805, respectively, by using layers 812 and 813 of a second adhesive, which is releasable at elevated temperature. Exemplary second metal foils may be made of copper at a thickness of about 3 μm. In step 892, second metal foils 810 and 811 are patterned in order to create a plurality of fiducials, which are used to mark spaces 820 and 821 reserved for attaching semiconductor chips.
In process step 893, a plurality of semiconductor chips 830 and 831 is attached to the second adhesive 812 and 813 on the first metal 804 and 805 within the reserved spaces 820 and 821, respectively. Chips 830 and 831 are oriented so that the chip terminals 832 and 833 face the respective second adhesive layer.
In process step 894 of
In process step 895, lamination material 840 and chips 830 and 831 are flattened uniformly by a leveling or grinding method until both the lamination material and the chip back sides have a planar surface across the panel. By this leveling process, the assemblies on both sides of the panel are completed and have planar surfaces.
In process step 896, the temperature is elevated to release the second adhesive of layers 812 and 813 on both sides of the panel and thus enable the separation of the panel core 801 with its adhering first metal foils 804 and 805 and layers 812 and 813 of second adhesives from the assemblies 850 and 851 on both panel sides. Each assembly is now freed to be processed separately.
During the processes summarized in step 997, the exposed terminal pads 833, lamination 840, chip 831, and fiducials 811 of panel 850 are plasma-cleaned. The plasma accomplishes, besides cleaning the surface from adsorbed films, especially water monolayers, some roughening of the surfaces; both effects enhance the adhesion of the sputtered metal layer. Then, at uniform energy and rate and while the panel is cooled from the back side, at least one layer 860 of metal is sputtered onto the exposed surfaces across the panel. The sputtered layer is adhering to the surfaces.
Preferably, the step of sputtering includes the sputtering of a first layer of a metal selected from a group including titanium, tungsten, tantalum, zirconium, chromium, molybdenum, and alloys thereof, wherein the first layer is adhering to chip and lamination surfaces; and without delay sputtering at least one second layer of a metal selected from a group including copper, silver, gold, and alloys thereof, onto the first layer, wherein the second layer is adhering to the first layer. The sputtered layers have the uniformity, strong adhesion, and low resistivity needed to serve, after patterning, as conductive traces for rerouting; the sputtered layers may also serve as seed metal for plated thicker metal layers.
After photomasking portions of chip 831 in step 998a, in optional step 998b at least one layer 861 of metal is electroplated onto the sputtered layers 860. A preferred metal is copper for its good conductivity. Next, step 999 in
In addition, it is preferred to deposit and pattern rigid insulating material 870, such as so-called solder resist, to protect and strengthen remaining chip areas not used for extended contacts and between the rerouting traces. In order to apply solder resist and other dielectric materials, photo-imagable materials, etchants, and others, a preferred technique uses an ultrasonic spray tool.
While this invention has been described in reference to illustrative embodiments, this description is not intended to be construed in a limiting sense. Various modifications and combinations of the illustrative embodiments, as well as other embodiments of the invention, will be apparent to persons skilled in the art upon reference to the description. It is therefore intended that the appended claims encompass any such modifications or embodiments.
This application claims priority to U.S. Provisional Application No. 61/842,151 filed on Jul. 2, 2013. Said application incorporated herein by reference for all purposes.
| Number | Date | Country | |
|---|---|---|---|
| 61842151 | Jul 2013 | US |
