Claims
- 1. A semiconductor structure:a) a well region formed in said semiconductor substrate; and b) a well edge implant, said well edge implant formed at the edge of said well region in said semiconductor substrate, wherein said well edge implant is formed under a shallow trench isolation, wherein said well edge implant comprises a P+ type implant and wherein said well region comprises a N type well region.
- 2. A semiconductor structure:a) a well region formed in said semiconductor substrate; and b) a well edge implant, said well edge implant formed at the edge of said well region in said semiconductor substrate, wherein said well edge implant is formed under a shallow trench isolation, wherein said well edge implant comprises a N+ type implant and wherein said well region comprises a P type well region.
- 3. A semiconductor structure comprising:a) a semiconductor substrate; b) a well formed in said semiconductor substrate, said well having an exterior perimeter and a substantially planer bottom; c) a self-aligned well edge implant formed at said exterior perimeter of said well, said self-aligned well edge implant being self aligned with said exterior perimeter of said well, wherein said self-aligned well edge implant comprises a P+ type implant and wherein said well comprises a N type well; and d) a shallow trench isolation region, and wherein said self-aligned well edge region is formed under said shallow trench isolation.
- 4. A semiconductor structure comprising:a) a semiconductor substrate; b) a well formed in said semiconductor substrate, said well having an exterior perimeter and a substantially planer bottom; c) a self-aligned well edge implant formed at said exterior perimeter of said well, said self-aligned well edge implant being self aligned with said exterior perimeter of said well, wherein said self-aligned well edge implant comprises a N+ type implant and wherein said well comprises a P type well; and d) a shallow trench isolation region, and wherein said self-aligned well edge region is formed under said shallow trench isolation.
- 5. The semiconductor structure of claim 3 wherein said self-aligned well edge implant comprises a loop of implant region.
- 6. The semiconductor structure of claim 3 wherein said self-aligned well edge implant is formed inside said well with an edge of said self-aligned well edge implant aligned with the exterior perimeter of said well.
- 7. The semiconductor structure of claim 4 wherein said self-aligned well edge implant comprises a loop of implant region.
- 8. The semiconductor structure of claim 4 wherein said self-aligned well edge implant is formed inside said well with an edge of said self-aligned well edge implant aligned with the exterior perimeter of said well.
RELATED APPLICATIONS
This application is a divisional of the earlier patent application by Baker, et al. entitled “Method and Structure to Reduce Latch-up Using Edge Implants”, Ser. No. 08/852,466, filed May 7, 1997, and now U.S. Pat. No. 5,861,330 that is incorporated herein by reference.
This application is related to the following co-pending U.S. patent applications, Ser. No. 08/715,288, for “Low ‘K’ Factor Hybrid Photoresist,” and Ser. No. 08/715,287, for “Frequency Doubling Photoresist,” both filed Sep. 16, 1996.
US Referenced Citations (15)