A Wafer Scale fail Bit analysis System for VLSI Memory Yield Improvement, Sakai et al Proc. IEEE 1990 Int. Conference on Microelectronic Test Structures, vol. 3, Mar. 1990, 175-178. |
Automatic In-Line Measurement for the Identification of Killer defects, Wilson et al, 1994 IEEE, pp. 5/1-5/8, Apr. 1994. |
Automatic Defect Classification System for Patterned Semiconductor Wafers Breaux et al. �Jul. 1995! IEEE International Symposium on Semiconductor Manufacturing, 68-73. |
Role of In-Line Defect Sampling Methodology in Yield Management, Nurani et al, Jul. 1995, International Symposium on Semiconductor Manufacturing, 243-247. |
Automatic in-Line to end-of-line defect correlation using FSRAM test structure for quick killer defect identification, Wilson et al, 1994 IEEE, vol. 7, Mar. 94, 160-163. |
A Spot-Defect to fault Collapsing Technique, Di et al, 1991 IEEE, pp. 580-583, Jun. 1991. |
A fuzzy Logic Expert System for Automatic Defect Classification of Semiconductor Wafer defects, Laria et al, 1994 IEEE, pp. 2100-2106, Jun. 1991. |
Simulating IC Reliability with Emphasis on Process-Flaw Related Earlyfailures Moosa et al, IEEE Transactions on Reliability, vol. 44, Nov. 4, 1995, 556-561. |