Patent Application
20080102648
The present disclosure relates in general to semiconductor fabrication and, more particularly, to a method and system for patterning photo-resists with reduced footing and scum residue.
In integrated circuit (IC) manufacturing technology, a resist layer is typically applied to a semiconductor wafer surface, followed by exposure of the resist through a mask. A post-exposure baking process and a developing process are then performed to form a patterned resist layer with openings. After verification that the resist is within fabrication specifications, the wafer is etched to remove portions of the wafer exposed through the openings. Following etching of the wafer, the resist layer is stripped.
In conventional resist patterning, it is not uncommon for a photo-resist footing and/or residual scum to be present in the openings of the patterned resist layer. That is, the photo-resist patterning and developing process commonly leaves a residue in the openings. This residue can narrow the resist opening as well as negatively affect the accuracy of critical dimension (CD) measurements and disturb etching bias tuning.
It would therefore be desirable to have a method and system of patterning and developing a photo-resist layer on a semiconductor wafer substantially free of photo-resist footing, scum, and/or other undesirable photo-resist residue.
Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is emphasized that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. It is also emphasized that the drawings appended illustrate only typical embodiments of this invention and are therefore not to be considered limiting in scope, for the invention may apply equally well to other embodiments.
For the purposes of promoting an understanding of the principles of the invention, reference will now be made to the embodiments, or examples, illustrated in the drawings and specific language will be used to describe the same. It will nevertheless be understood that no limitation of the scope of the invention is thereby intended. Any alterations and further modifications in the described embodiments, and any further applications of the principles of the invention as described herein are contemplated as would normally occur to one skilled in the art to which the invention relates. Furthermore, the depiction of one or more elements in close proximity to each other does not otherwise preclude the existence of intervening elements. Also, reference numbers may be repeated throughout the embodiments, and this does not by itself indicate a requirement that features of one embodiment apply to another embodiment, even if they share the same reference number.
Disclosed is a method of patterning a semiconductor substrate or other device layer substantially free of resist residue. In this regard, the disclosed method reduces the presence of resist footings and/or scum layers in the openings of a patterned resist layer. The disclosed method includes application of a buffer layer that is applied to a top surface of a substrate followed by application of a resist layer on the buffer layer. Portions of the buffer and resist layers are removed simultaneously during a developing process to define various openings in the resist layer and buffer layer.
The method 100 begins at step 102 by providing a substrate 202 or other base layer, as illustrated in
The substrate 202 may also include a material layer (not shown) formed thereon that includes a dielectric material such as silicon oxide, silicon nitride, a low dielectric constant (low k) material, or a combination thereof. The low k material may include fluorinated silica glass (FSG), carbon doped silicon oxide, Black Diamond® (Applied Materials of Santa Clara, Calif.), Xerogel, Aerogel, amorphous fluorinated carbon, Parylene, BCB (bis-benzocyclobutenes), SiLK (Dow Chemical, Midland, Mich.), polyimide, and/or other materials as examples. A process of forming the material layer may utilize chemical vapor deposition (CVD) or a spin-on coating.
The method 100 proceeds to step 104 by depositing a buffer layer 204 on the substrate 202. The buffer layer, in a manner similar to formation of a resist layer, may be formed using spin-on coating or other applicable technique. The buffer layer may include a bottom anti-reflection layer (BARC) or component. One or more adhesion layers may be formed on the top and bottom surfaces of the BARC layer to enhance adhesion between the buffer layer 204 and the substrate 202 and a resist layer 206,
The method 100 continues to step 106 with coating of a photoresist (resist) layer 206 on the buffer layer 204, as illustrated in
The method 100 proceeds to step 108 wherein the resist layer 206 on the substrate 202 is patterned, by a lithography process including exposing the buffer and resist layers to a radiation beam. The radiation beam may be a photon beam. For example, the resist layer on a semiconductor wafer may be exposed to an ultraviolet (UV) light through a mask (not shown) having a predefined pattern that defines desired openings. The exposing process may be implemented using a stepper by a step-and-repeat method or using a scanner by a step-and-scan method. Other options to the radiation beam other than photon beams include electron beam and ion beam. For example, the resist layer and the buffer layer may be exposed to an electron beam (e-beam) by an e-beam exposure system (e-beam writer). A pattern may be written to the resist layer according to a predefined pattern using the e-beam writer. The exposing process may be further extended to include other technologies such as a maskless exposing or writing process.
Referring to
The lithography processes described above may only present a subset of processing steps associated with a lithography patterning technique. The lithography process may further include other steps such as cleaning and baking in a proper sequence. For example, the developed resist and buffer layers may be further baked, referred to as hard baking.
In accordance with conventional fabrication techniques, the method 100 then proceeds to step 110 wherein the substrate 202 is etched. Thereafter, the buffer layer 204 and the resist layer 206 may be removed at 112 by a process such as wet stripping or plasma ashing.
It is recognized that a number of PAGs may be used with the present invention. For example, the commercial product referred to as TPS C4 is one exemplary PAG component that can be used to decompose the buffer layer. As such, it is recognized that other PAG components may be used, such as that described in U.S. Pat. No. 5,648,196 which discloses a water soluble photoacid generator that is formulated with a p-hydroxystyrene polymer and a water soluble sugar. In U.S. Pat. No. 5,648,196, the disclosure of which is incorporate herein by reference, one exemplary PAG component is dimethylarylsulfonium salt wherein the aryl group has one or more hydroxy constituents. Other exemplary PAG components include odium salts including diphenyliodonium salts and triphenylsulfonium salts, halogen compounds, and o-nitrobenityl esters such as 2-nitrobenzylsulfonic acid ester. One skilled in the art will appreciate that the listed PAG components usable with the present disclosure are not exhaustive and that other PAG components not specifically identified may be used. Additionally, it is recognized that the PAG component may be selected to achieve a desired diffusion length. That is, if a long diffusion length is desired, a small molecular size PAG is preferably used whereas for a short diffusion length, a bulky PAG is preferably used.
A suitable developer that may be used to remove the exposed portions of the resist and buffer layers is tetramethyl ammonium hydroxide (TMAH). However, other developers are contemplated.
It is recognized that a number of material(s) may be used for composition of the buffer layer. In one example, the buffer layer is formed of a relatively thin polymer containing Lactone, compounds with an —OH functional group, compounds with a —COOH functional group, or the like that absorb acid released by the photo-resist layer 206 in such a manner that causes affected regions of the buffer layer 204 to be dissolvable by an appropriate developer, such as TMAH.
Therefore, in one exemplary embodiment, the present invention is directed to a process of patterning a semiconductor device. The semiconductor device is patterned by depositing a thin resist or buffer layer on a substrate film followed by depositing of a photo-resist layer on the buffer layer. The photo-resist layer includes an acid generating component that is activated during exposure of the photo-resist layer. Thus, during exposure of the photo-resist layer, acid or other agent is released by the photo-resist layer and diffuses into portions of the buffer layer. The agent is absorbed by the buffer layer and decomposes affected regions of the buffer layer during post-exposure baking thereby making the affected regions dissolvable by a suitable developer that can be applied to simultaneously remove exposed portions of the photo-resist layer and the buffer layer.
It is to be understood that the following disclosure provides different embodiments, or examples, for implementing different features of various embodiments. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not itself dictate a relationship between various embodiments and/or configurations discussed.
