Patent Application
20090109595
The present invention relates generally to the field of substrate processing equipment. More particularly, the present invention relates to a method and apparatus for performing electrostatic chucking of a semiconductor substrate wafer. Merely by way of example, the method and apparatus of the present invention are applied to clamp and declamp a semiconductor wafer on an electrostatic chuck for ambient thermal processing in a track lithography tool. The method and apparatus can be applied to other processing devices for semiconductor processing equipments utilized in other processing chambers.
Modem integrated circuits contain millions of individual elements that are formed by patterning the materials, such as silicon, metal and dielectric layers, that make up the integrated circuit to sizes that are small fractions of a micrometer. The technique used throughout the industry for forming such patterns is photolithography. A typical photolithography process sequence generally includes depositing one or more uniform photoresist (resist) layers on the surface of a substrate, drying and curing the deposited layers, patterning the substrate by exposing the photoresist layer to radiation that is suitable for modifying the exposed layer and then developing the patterned photoresist layer.
It is common in the semiconductor industry for many of the steps associated with the photolithography process to be performed in a multi-chamber processing system (e.g., a cluster tool) that has the capability to sequentially process semiconductor wafers in a controlled manner. One example of a cluster tool that is used to deposit (i.e., coat) and develop a photoresist material is commonly referred to as a track lithography tool.
Track lithography tools typically include a mainframe that houses multiple chambers (which are sometimes referred to herein as stations) dedicated to performing the various tasks associated with pre- and post-lithography processing. There are typically both wet and dry processing chambers within track lithography tools. Wet chambers include coat and/or develop bowls, while dry chambers include thermal control units that house bake and/or chill plates for supporting and retaining semiconductor wafers or other work-pieces in a stationary position during thermal processing. In order to secure the semiconductor wafers on the plates, the plates are generally configured as a type of chuck using either electrostatic force or vacuum. However, one potential problem is that if a substrate wafer is loaded directly onto the upper surface of a conventional electrostatic chuck during substrate processing, the chuck surface can abrade the material present on the backside of the substrate wafer, resulting in the introduction of particulate contaminants to the process environment. The particulate contaminants can adhere to the backside of another substrate wafer and be carried to other process environment or cause defects in the circuitry fabricated upon the substrate wafer. As the semiconductor device geometry has become smaller with each generation of ICs, these particulate contaminants can cause a loss in yield as well as degradation of device characteristics and reliability.
One method of reducing the number of particles generated on the backside of the substrate wafer is to reduce the contact area between the substrate wafer and the surface of the electrostatic chuck. This can be accomplished by, for example, using an array of proximity pins or support members that space the substrate at a predetermined distance from the surface of the electrostatic chuck. However, unlike a conventional electrostatic chuck usually used in vacuum systems, two major differences exist when trying to implement an electrostatic chuck for track lithography tool applications: both the ambient gas pressure and the gap between the substrate wafer and the surface of an electrostatic chuck with proximity pins are much higher than for conventional electrostatic chucks in vacuum applications. Because of the proximity pins, the gap is in a range from 50 μm to 100 μm, which is at least one order magnitude larger than a conventional “direct-contact” type chuck. Additionally, the pressure during thermal processing in track lithography tools may be as high as one atmosphere and a certain humidity level also exists in the process chamber. Under such ambient conditions with humidity, the chucking force based on traditional techniques have been found to be significantly reduced, resulting in unsecured clamping of the substrate wafer.
Thus, there is a need in the art for improved methods and apparatuses for performing electrostatic chucking of semiconductor wafers during thermal processing operations in ambient air within the track lithography tool.
According to embodiments of the present invention, techniques related to the field of substrate processing equipment are provided. More particularly, the present invention relates to a method and apparatus for performing electrostatic chucking of a semiconductor substrate wafer. Merely by way of example, the method and apparatus of the present invention are applied to clamp and declamp a semiconductor wafer on an electrostatic chuck for ambient thermal processing in a track lithography tool. The method and apparatus can be applied to other processing devices for semiconductor processing equipments utilized in other processing chambers.
In a specific embodiment, the invention provides a method of clamping and declamping a semiconductor wafer on an electrostatic chuck in ambient air. The method includes disposing a semiconductor wafer at a predetermined distance above a dielectric surface of the electrostatic chuck having one or more electrodes and applying a first voltage to the one or more electrodes of the electrostatic chuck for a first time period. The first voltage is greater than a predetermined threshold. The method further includes reducing the first voltage to a second voltage after the first time period. The second voltage is substantially equal to a self bias potential of the semiconductor wafer. Additionally, the method includes maintaining the second voltage for a second time period and adjusting the second voltage to a third voltage. The third voltage is characterized by a polarity opposite to that of the first voltage and a magnitude smaller than the predetermined threshold. Moreover, the method includes reducing the third voltage to a fourth voltage after a third time period. The fourth voltage is substantially equal to the second voltage.
In certain specific embodiments, the method provided by the invention further includes disposing a second semiconductor wafer on the electrostatic chuck after replacing the first semiconductor wafer. Furthermore, the method includes applying a fifth voltage to the one or more electrodes for chucking the second semiconductor wafer. The fifth voltage is characterized by a polarity opposite to the first voltage and a magnitude greater than the predetermined threshold.
In another specific embodiment, the invention provides a method of performing electrostatic chucking of a semiconductor wafer in ambient air. The method includes providing an e-chuck in a chamber with ambient air. The e-chuck includes one or more electrodes and a dielectric plate with a plurality of proximity pins. The method further includes applying a first voltage greater than a predetermined threshold to the one or more electrodes for a first time period and disposing a semiconductor wafer on the dielectric plate such that a separation between the semiconductor wafer and the dielectric plate is reduced until at a time when the semiconductor wafer is in contact with the plurality of proximity pins. The method further includes reducing the first voltage to a second voltage after the first time period. The second voltage is substantially equal to a self-bias potential of the semiconductor wafer. Additionally, the method includes maintaining the second voltage for a second time period and changing the second voltage to a third voltage. The third voltage is characterized by a first polarity opposite to that of the first voltage and a first magnitude greater than the predetermined voltage threshold. Moreover, the method includes switching the third voltage after a third time period to a fourth voltage. The fourth voltage is characterized by a second polarity opposite to that of the third voltage and a second magnitude smaller than the predetermined voltage threshold. Furthermore, the method includes adjusting the fourth voltage after a fourth time period to a fifth voltage. The fifth voltage is substantially equal to the second voltage.
In an alternative embodiment, the invention provides a track lithography tool that includes a process chamber and an electrostatic chuck disposed in the process chamber. The electrostatic chuck includes a dielectric plate and one or more electrodes. The track lithography tool also includes one or more capacitance sensors disposed on the dielectric plate and a transfer robot configured to position a conductive wafer at a predetermined distance above the dielectric plate. The track lithography tool further includes a power supply configured to apply a voltage to the one or more electrodes. The power supply includes a computer-readable medium storing a plurality of instructions for controlling a data processor to adjust the voltage. The plurality of instructions additionally includes instructions that cause the data processor to adjust the voltage to a first voltage for a first time period. The first voltage is greater than a predetermined threshold. The plurality of instructions includes instructions that cause the data processor to reduce the first voltage to a second voltage after the first time period. The second voltage is substantially equal to a self bias potential of the semiconductor wafer. The plurality of instructions also includes instructions that cause the data processor to maintain the voltage at the second voltage for a second time period and instructions that cause the data processor to adjust the second voltage to a third voltage characterized by a polarity opposite to that of the first voltage and a magnitude smaller than the predetermined threshold. The plurality of instructions further includes instructions that cause the data processor to reduce the third voltage to a fourth voltage after a third time period. The fourth voltage is substantially equal to the second voltage.
In yet another alternative embodiment, a track lithography tool is provided to include a process chamber and a bipolar electrostatic chuck disposed in the process chamber. The bipolar electrostatic chuck includes two electrodes and a dielectric plate with a plurality of proximity pins. The track lithography tool further includes one or more capacitance sensors disposed on the dielectric plate and a transfer robot configured to dispose a conductive wafer on the dielectric plate such that a separation between the conductive wafer and the dielectric plate is reduced until the conductive wafer is in contact with the plurality of proximity pins. Additionally, the track lithography tool includes a power supply configured to apply a voltage to each of the two electrodes and a controller coupled to the power supply. The controller includes a computer-readable medium storing a plurality of instructions for controlling a data processor to adjust the voltage. The plurality of instructions includes instructions that cause the data processor to adjust the voltage to a first voltage greater than a predetermined threshold for a first time period. The plurality of instructions includes instructions that cause the data processor to reduce the first voltage to a second voltage after the first time period. The second voltage is substantially equal to a self-bias potential of the semiconductor wafer. Additionally, the plurality of instructions includes instructions that cause the data processor to maintain the second voltage for a second time period and instructions that cause the data processor to change the second voltage to a third voltage characterized by a first polarity opposite to that of the first voltage and a first magnitude greater than the predetermined threshold. The plurality of instructions further includes instructions that cause the data processor to switch the third voltage after a third time period to a fourth voltage characterized by a second polarity opposite to that of the third voltage and a second magnitude smaller than the predetermined threshold. Moreover, the plurality of instructions includes instructions that cause the data processor to adjust the fourth voltage after a fourth time period to a fifth voltage. The fifth voltage is substantially equal to the second voltage.
Depending upon the embodiment, many benefits can be achieved, particularly for achieve enhanced chucking pressure for clamping semiconductor wafer on a bipolar electrostatic chuck in ambient environment where the pressure can be as high as one atmosphere with certain humidity and the wafer-to-chuck gap distance is unusually one or two orders of magnitude larger than conventional chucks. These and other benefits may be described throughout the present specification and more particularly below.
The two electrodes are made of electrical conductors and configured to receive voltages adjustable both in polarity and a wide range of magnitudes from an external power supply (not shown). For example. a voltage Ve is applied to each of the two electrodes 30. For the bipolar electrostatic chuck, the voltage on Electrode A has an opposite polarity to the voltage on Electrode B. For symmetric electrodes, the voltage magnitude on Electrode A can be the same as the voltage magnitude on Electrode B. The semiconductor wafer 10 usually can be grounded with a potential of Vw˜0. In certain embodiment, if a monopolar electrostatic chuck is used, an additional plasma environment may be used in the vicinity between the wafer and dielectric plate for assisting electrostatic chucking. The plasma may induce a non-zero self bias potential Vw≠0 for the wafer. The potential difference between the electrode and wafer Ve-Vw would induce a build-up of static charge on the surface of wafer and electrodes. For example, charges 111 form on one region of the lower surface 11 of the wafer 10 and correspondingly charges 101 with opposite sign form on the opposing surface of the Electrode A. Similarly, charges 102 form on another region of the lower surface 11 of the wafer 10 and correspondingly charges 102 with opposite sign form on the opposing surface of the Electrode B. These static charges with opposite signs create an electric field across the distance L (including the gap-distance (L−d) and the dielectric plate thickness (d)). Because of the opposite polarity of the applied voltages on the two electrodes, the sign of charges 101 is opposite to charges 102, and the sign of charges 111 is opposite to charges 112.
In one embodiment, the dielectric plate of the bipolar electrostatic chuck 20 is made of materials characterized by high dielectric constant and high resistivity. However, even with electric insulators, certain vertical charge motion may still occur when the voltage Ve is applied, resulting in charges 121 and 122 to some extent on the corresponding regions of the upper surface 21 of the dielectric plate. These charges 121 and 122 (having an opposite sign versus 121) result in a surface potential Vs for the surface 21. Theoretically all the charges on the surface 11, surface 21, and surfaces of Electrode A and Electrode B are static induced so that following relationship holds,
σe+σs+σw=0 (Eq. 1)
where σe denotes the charges on either Electrode A or Electrode B (for example charges 101 or 102), σs the charges on the surface of dielectric plate (for example charges 121 or 122), and σw the charges on the wafer surface (for example, charges 111 or 112). Using the definition of voltage drop,
V({right arrow over (r)})=−∫∞r{right arrow over (E)}·{right arrow over (ds)} (Eq. 2)
we obtain the voltage potential at the surface of the dielectric plate
and the voltage potential at the wafer surface
where κ is the dielectric constant of the dielectric plate relative to that of air. After some manipulation, the charges induced on the lower surface of the wafer can be represented as
The electric field corresponding to the induced charges on the wafer surface is then
Subsequently, the electrostatic chucking pressure associated with the electric field and charges is
with the negative sign simply meaning that the pressure P is in the opposite direction to the electric field direction. As shown in
In another embodiment of the application of electrostatic wafer chucking in a track lithography tool, the semiconductor wafer is eventually supported by, at least partially, a plurality of proximity pins (not shown) on the dielectric plate. Each of the plurality of proximity pins can be made from a sapphire ball (or other material) being partially embedded in a slot or other orifice on the surface of the dielectric plate and partially protrudes with a certain height. In a specific embodiment, as the wafer is supported by the plurality of proximity pins, most area of the lower surface of the wafer is separated from the surface of the dielectric plate by a distance. In fact the distance is the gap-distance (L−d) defined in
As seen above, the gap-distance (L−d) for a wafer to be held on an electrostatic chuck in track lithography tool is about two orders of magnitude larger than conventional wafer-to-chuck gap. If a conventional chucking voltage is applied, the resulted chucking force may be too small to properly hold the wafer. On the other hand, unlike the conventional electrostatic chuck operated in vacuum, the absolute pressure in the gap or the vicinity of the wafer 10 and surface 21 can be as high as 1 atm of ambient air in a thermal processing chamber of track lithography tools. The chucking forces are found to be significantly reduced at ambient conditions as compared to the vacuum case, as pointed out by G. Kalkowski in a published article (Microelectronic Engineering, Vol 61-62, (2002), pp 357-361). However, embodiments of the present invention provide novel methods and apparatus to overcome the problem with reduced chucking forces for large wafer-to-chuck gap distance and high pressure. More details about the methods and apparatus for chucking a semiconductor wafer on an electrostatic chuck with a large gap in ambient air can be found through this specification and in particular below.
Because a high pressure exists in the air gap between the wafer and electrostatic chuck, as the voltage applied to the electrodes become higher (with an intention to induce more static charges), it is possible that an electric breakdown of the air between the lower surface 11 of the semiconductor wafer 10 and the upper surface 21 of the dielectric plate will occur. The electric breakdown simply turns insulating air into a conductive media to have a steady state charge transfer across the air gap.
Referring to
As shown in
In one embodiment, as Ve further increases, the amount of charges 125 and 126 may increase unless the voltage Ve is still much lower than the dielectric strength of the dielectric plate to cause its dielectric breakdown. In another embodiment, the voltage Ve on the electrodes is quickly reduced to approximate zero (i.e., Ve˜0) as part of the chucking sequence after being maintained at a level above the voltage threshold Vth for a time period. The wafer is still at potential zero by grounding (Vw=0). As the voltage Ve drops to zero, static charges will move to the lower surface of the wafer while the charges on the upper surface of dielectric plate will mostly be retained due to the high resistivity of the dielectric plate. Therefore, the electric field induced by these static charges between the wafer and the dielectric plate becomes the source of the attractive chucking force. As shown in
where σs denotes as the static charges retained on the surface of the dielectric plate. Since the charges σs on the surface of dielectric plate built up through air breakdown charge transfer can be much larger in quantity than those simply caused by charge motion within the dielectric plate due to non-ideal insulation. The resulting chuck pressure P can be sufficiently high to hold the semiconductor wafer even with the large gap-distance and high pressure.
Compared to a conventional case with the chuck voltage as high as the Paschen observed breakdown voltage VB and a same gap-distance (L−d), the chuck pressure reaches a maximum as in the following form,
It is interesting to compare the results of Eq. 8 and Eq. 9. As an example, the pressure associated with a voltage Ve=VB=800 V with the wafer at potential zero, for a typical values of d=50 microns, L=150 microns, κ=2.1, then the chucking pressure with no surface charge is obtained using Eq. 9, i.e., P=180 Pa. But when the charges are brought to the surface of the dielectric plate by first turning on electrostatic chucking power with Ve greater than air breakdown threshold before (or after) the wafer touches the proximity pins for a short time period then turning off the power to bring Ve back to zero (Ve=Vw=0), these surface charges, assuming they correspond to 800 V potential difference, should provide 280 Pa of chucking pressure based on Eq. 8.
In an embodiment, by using a high resistivity dielectric for the electrostatic chuck, the charges built up on the surface of the dielectric plate remains relatively immobile for a time period during which the wafer can be chucked on for any relevant processing including but not limiting to lithography, ion implantation, plasma etching, film deposition, and thermal treatment. For example, the dielectric plate of the electrostatic chuck can be made of Kapton polyimide. In another example, it can be made of other high strength dielectric like sapphire. The time period for retaining those charges can be reasonably achieved to be greater than typical wafer process times. For example, the time period is at least 1 to 2 minutes. In another embodiment, the amount of charges may depend on how many charges are transferred, and on the uniformity of the breakdown across the wafer-to-chuck gap. Of course, there can be many alternatives, variations, and modifications.
In order to illustrate one of the novel features of the chucking/dechucking sequence,
The method 400 also includes a process of applying first voltage greater than a predetermined threshold to the electrostatic chuck for a first time period (Process 412). In one embodiment, the applying first voltage starts after a time t1 from the Wafer-Down time, as shown in
The method 400 further includes a process of reducing the first voltage to a second voltage after the first time period (Process 414). In one embodiment, the second voltage is substantially equal to a self bias potential of the first semiconductor wafer. In particular, the semiconductor wafer typically is grounded when bipolar electrostatic chuck is used. In this case, the second voltage is approximate zero, as shown in
The method 400 additionally includes a process of maintaining the second voltage for a second time period (Process 416). As described earlier part of this specification, the chucking voltage pulse applied in Process 414 create static charges on the dielectric surface by taking advantage of air breakdown charge transfer across the wafer and the dielectric plate. As the first voltage is brought down to approximate zero, the static charges contribute to an enhanced chucking force to hold the wafer onto the chuck. In one embodiment, the process 416 is to keep the wafer in a chucking state while one or more wafer treatment processes are performed. For example, these processes include but are not limited to lithography, ion implantation, plasma etching, film deposition, and thermal treatment. In one example, the second time period for performing these processes may be 1 or 2 minutes.
The method 400 further includes a process of adjusting the second voltage to a third voltage which is characterized by a polarity opposite to the first voltage and a magnitude smaller than the predetermined threshold (Process 418) and followed by a process of reducing the third voltage to a fourth voltage after a third time period (Process 420). The process 418 basically starts a dechucking sequence to reduce the electrostatic chucking force holding the semiconductor wafer so that the wafer can be removed from the chuck. In one embodiment, adjusting the second voltage to a third voltage for a third time period is to apply a dechucking voltage pulse characterized by an opposite polarity to the chucking pulse and a magnitude V3 as well as a pulse width t3. In particular, as shown in
In an specific embodiment, the magnitude V3 is selected such that the combined voltage potential difference, i.e., the third voltage plus the residue charge induced potential difference, would be higher than the voltage threshold (while with a negative sign). In other words, Paschen breakdown for the air in the gap can occur between the surface of dielectric plate and the lower surface of the wafer, effectively moving the residue charges to the wafer. For example, if the residue charges correspond to a potential −500 V, a maximum voltage for chucking is V2, then the dechucking voltage may be chosen to be −(500 V+(V2−Vth)). Of course, there can be other variations, alternatives, and modifications in detail selection of the dechucking voltage in response to the chucking voltage applied earlier and a desired amount of residual charges on the dielectric surface. According to an embodiment, the residual charges on the surface of the dielectric plate can be measured and real-time monitoring can be performed using a plurality of electrical (capacitance) sensors. These sensors can detect and provide information regarding whether the chucking is complete or dechucking sequence has properly released the wafer. In yet another specific embodiment, the dechucking pulse is also controlled by its pulse width, i.e., the third time period t3, so that most residue charges on the surface of the dielectric plate are substantially drained off or at least not many left there. In addition, after t3, the third voltage is brought down quickly to a fourth voltage so that the surface will not be re-charged with an opposite sign; and the fourth voltage essentially is approximate zero (with the DC power supply being turned off). Similar to the case of applying chucking voltage pulse, the DC power supply can be configured to apply dechucking voltage pulse or reduce it back to approximate zero with a time constant substantially shorter than the pulse width t3.
Finally, as the dechucking process is done after Process 420, the method 400 includes removing the semiconductor wafer from the electrostatic chuck (Process 422) followed by other processes including reloading a second wafer for essentially the same wafer treatment. In one embodiment, after going through the chucking/dechucking of each wafer on these bipolar chucks, the initial chucking voltage applied to any wafer loaded next is preferred to have a reversed polarity versus the applied chucking voltage for the last wafer. Because the dechucking sequence usually may not be able to completely drain off all static charges on the surface of the dielectric plate, the reversion of voltage polarity from one wafer to the next can eliminate long term drift in the chucking force due to buildup of the residue charges with one particular sign on the surface of the dielectric plate.
In one embodiment, the dechucking pulse height V3 surpassing the predetermined voltage threshold for a time period t3 (dechucking pulse width) is to erase a memory of any surface charge leakage through the dielectric plate due to relatively lowered resistivity at elevated temperatures or simply non-uniformity of charge distribution after long processing time. With such a dechucking voltage pulse V3 applied for the time period t3, the charges remained on the dielectric surface are transferred in the opposite direction in an amount that is controlled by the threshold voltage only, not by any potential induced by pre-existing charges from leakage. Therefore, the thereafter followed forward pulse at time period t4, which essentially is similar to the single dechucking voltage pulse applied in case shown in
The method 600 also includes applying a chucking voltage greater than a predetermined voltage threshold to the one or more electrodes (Process 612) for a time period t2 and disposing a semiconductor wafer on the dielectric plate (Process 614). In one embodiment, the chucking voltage is supplied by a DC power supply coupled to the one or more electrodes. The DC power supply is controlled by a coupled controller which includes a computer-readable medium storing a plurality of instructions for controlling a data processor to adjust the power supply voltage. For example, some of the plurality of instructions to the data processor include applying the chucking voltage with controlled timing, voltage polarity, voltage magnitude, time constant for changing from one magnitude to another, and the like. In one example, the voltage polarity is positive for Electrode A but negative for Electrode B when a bipolar electrostatic chuck is used. In other example (when performing chucking a different wafer), the voltage polarity may be reversed. The predetermined voltage threshold is a function of a Paschen air breakdown voltage depending on the pressure P in the chamber in the vicinities of the chuck and wafer as well as a gap-distance d′ when the wafer is chucked on the electrostatic chuck. In particular, on the one hand the chucking voltage should be sufficiently higher than the predetermined voltage threshold to induce an electric breakdown in the air gap between the wafer and chuck. On the other hand the chucking voltage should be still substantially smaller than a dielectric constant of the dielectric plate so that there is no shorting between the surface of the dielectric plate and the one or more electrodes.
In another embodiment, the process 614 is a wafer loading process during which a transfer robot is used to handle the wafer and place it at various positions with predetermined distances above the dielectric plate. In certain embodiments, the dielectric plate of the e-chuck includes a plurality of proximity pins made of sapphire balls partially embedded in the upper surface of the dielectric plate. In one example, the process 614 includes placing the wafer into a final position so that at least some points of the lower surface of the wafer is supported by some of the plurality of proximity pins and rest area of the lower surface is separated by variable distances depending on extent of wafer warpage and variation in heights of the proximity pins. In the wafer loading process, the wafer-to-chuck gap distances at various positions, including the final position, can be monitored in real time and signals of the gap distances are sent to the same data processor used for controlling the DC power supply.
In a specific embodiment, the method 600 including performing the process 612 at a certain time before or after the process 614. In one example, referring back to
After the time period t2, with the chuck voltage being maintained at the magnitude V2, the method 600 includes a process of reducing the voltage from V2 down to a second voltage level substantially equal to a self bias potential of the semiconductor wafer (Process 616). In one embodiment, an amount of static charges is transferred from the semiconductor wafer to the dielectric plate during the time period t2 as the applied chucking voltage achieves the magnitude V2. As the chucking voltage equals to the self bias potential of the semiconductor wafer, there is basically zero potential difference between the semiconductor wafer and the one or more electrodes, thereby effectively stopping further charge transfer. In a specific embodiment, the voltage is reduced by controlling the DC power supply under certain instructions preloaded in a data processor which is continuously updated with information associated with the self bias potential of the semiconductor wafer, an average gap distance, a capacitance between the wafer and the dielectric plate, and the like. Depending on the structural design the electrostatic chuck and the physical and electronic environment around the wafer, the self bias potential of the semiconductor wafer can be zero or a non-zero value. In another specific embodiment, the operation of the process 616 is associated with a time constant substantially smaller than the time period t2, so that a substantial portion of static charges can be retained on the surface of the dielectric plate. As shown in
Followed by the process 616, the static charges retained on the surface of dielectric plate can induce charges with opposite signs on an opposing region of the lower surface of the wafer, creating a static electric field that results in an enhanced chucking force sufficiently large to hold the wafer on the e-chuck. The method 600 includes maintaining the second voltage level at the self bias potential of the semiconductor wafer for another time period (Process 618). In one example, the self bias potential of the semiconductor wafer is zero so that the data processor can send certain instructions to keep the DC power supply off. During the time period, the static charges can be substantially retained on the surface of the dielectric plate without leaking to/from the electrodes due to high resistivity of the dielectric plate. In the mean time, the wafer will be chucked to the dielectric plate by the electrostatic chucking force and desired wafer processing can be performed. This time period typically can be as long as the wafer processing is performed, for example, 1 or 2 minutes and longer. In one example, the e-chuck is also a bake plate so that the wafer now can be treated thermally at elevated temperatures in an ambient environment within the processing chamber. The relatively large gap and high pressure between the lower surface of the wafer and the surface of the bake plate (i.e., the dielectric plate of the e-chuck) allows annealing characterized by more uniformity and with better thermal conduction than in conventional thermal processes. In another example, a lithography, etch, or other suitable process can be performed.
After the desired wafer processing is finished, the method 600 further includes applying a dechucking voltage pulse to the one or more electrodes (Process 620) and thereafter applying a forward voltage pulse to the one or more electrodes (Process 622). Applying a dechucking voltage essentially starts a dechucking process that reduces the electrostatic chucking force imposed on the wafer so that the wafer can be removed. According to certain embodiments, the process 620 includes applying the dechucking voltage pulse V3 with a pulse width t3 and a polarity opposite to the chucking voltage. In one embodiment, the process 620 is performed by the data processor to execute certain preloaded instructions to cause the DC power supply to change the second voltage level to V3 within a time constant substantially shorter than the pulse width t3. The magnitude of V3 is selected to be higher than the predetermined voltage threshold to initiate an air breakdown charge transfer between the lower surface of the wafer and the upper surface of the dielectric plate in a reverse direction compared to the earlier chucking process. This reverse charge transfer is able to at least partially cancel the retained static charges on the dielectric plate and also helps to remove a memory of any surface charge leakage through the dielectric plate due to relatively lowered resistivity at elevated temperatures or simply non-uniformity of charge distribution after long series of chucking/dechucking cycles. In one embodiment, the pulse width t3 and pulse height V3 can be adjusted by the data processor under certain pre-stored instructions to the DC power supply and based on amount of charges continuously sensed by a plurality of electric (capacitance) sensors.
After the time period of t3 associated with the pulse width of the dechucking voltage pulse, the remaining amount of charge on the surface of dielectric plate influences a capacitance value which is associated with the wafer-to-chuck gap distance. The capacitance value can be monitored by a plurality of capacitance sensors and be continuously sent to the data processor, which in turn determines how the subsequent forward pulse should be applied in Process 622. The forward pulse is characterized by a reverse polarity (compared to the dechucking pulse applied right before) and a pulse height V4 for a time period of t4 (i.e., the pulse width of the forward pulse). In one embodiment, the process 622 is performed by the data processor to execute certain preloaded instructions to cause the DC power supply to change the voltage from a magnitude V3 to another magnitude V4 with a reverse polarity within a time constant substantially shorter than the time period t3 or the time period t4. In another embodiment, the pulse height V4 of the forward pulse is adjusted based on the amount of remaining charges after the Process 620. In particular, the magnitude of V4 is selected so that a combined potential difference between the wafer and the e-chuck, including the voltage V4 plus the remaining-charge-induced potential difference, becomes just high enough to initiate another air breakdown charge transfer across the wafer-to-chuck gap during the time period t4. This air breakdown charge transfer occurs in a reverse direction compared to that induced by the dechucking voltage pulse during the time period t3, thereby helping draining off the remaining static charges on the surface of the dielectric plate.
Furthermore, the method 600 includes a process of adjust the voltage after the time period t4 from the magnitude V4 to a level substantially equal to a self bias potential of the semiconductor wafer (Process 624). In one embodiment, the self bias potential at this time is approximate zero and the voltage essentially is reduced to zero by turning off the DC power supply within a time constant substantially shorter than the forward voltage pulse width t4. In another embodiment, the process 624 is performed by monitoring the static charges on the surface of the dielectric plate by the plurality of capacitance sensors. Essentially, the pulse width t4 of the forward voltage pulse can be adjusted to control the air breakdown charge transfer during the time period t4 based on the remaining charge amount monitored by the capacitance sensors. In certain embodiments, both the dechucking voltage pulse and subsequent forward voltage pulse contribute to how the remaining charges on the dielectric plate are effectively drained off. In particular, combined input information associated with the charge amount, wafer-to-chuck gap-distance, air pressure, wafer warpage, and proximity pin height variations effectively determine how the DC power supply is controlled to generate output parameters for the dechucking/forward voltage pulses Though the charges may not likely or necessarily be completely removed due to non-uniformity or leakage from imperfect insulation, the chucking force between the wafer and the e-chuck is substantially reduced so that the wafer can be removed from the e-chuck.
Of course, the wafer chucking/dechucking methods according to embodiments of the present invention can be applied repeatedly in mass production. Certain embodiments of the invention includes to apply the initial chucking voltage to chuck the next wafer with a reversed polarity to that for chucking the last wafer. Advantages of this chucking polarity reversion lie in an effective elimination of long term drift in the chucking force due to buildup of the residue charges with one particular sign on the surface of the dielectric plate. Of course, other charge clean-up procedures can be performed as one of ordinary skilled would recognize many variations, alternative, and modifications.
As discussed above, one or ordinary skill in the art may recognize that the particular naming of the wafer, chuck, chamber, tool, proximity pin, power supply, sensor, data processor, and other aspects are not mandatory or significant. For example, the wafer may be a semiconductor wafer as mentioned in above specification for most typical applications. It also can be a metal wafer such as those used for making magnetic heads or a conductive substrate used for flat panel display. The size of the wafer, correspondingly the size of the e-chuck can vary, such as 100 mm, 125 mm, 200 mm, 300 mm, 400 mm or larger. The shape of the chuck or wafer is also not limited to circle or square or rectangular shape. The mechanisms that implement the invention or its features may have different names. One or ordinary skilled in the art may recognize that methods provided by the invention can be implemented as software, hardware, firmware or any combination of the three and is in no way limited to implementation in any specific programming language, or for any specific operating system or environment. Additionally, the apparatus or system that implements these electrostatic chucking sequences may include individual chambers, cluster tools, or in-line tools.
In a particular embodiment, the track lithography tool is used to form, through use of a coating process, an anti-reflection (AR) and a photoresist film on substrates, for example, semiconductor wafers. The track lithography tool is also used to perform a development process on the substrates after they have been subjected to a pattern exposure process. Additional processes performed on the track lithography tool, which may be coupled to an immersion scanner, include PEB and the like. The substrates processed by the track lithography tool are not limited to semiconductor wafers, but may include glass substrates for a liquid crystal display device, and the like.
The track lithography tool 700 illustrated in
The factory interface block 1 is a processing block for transferring unprocessed substrates received from outside of the track lithography tool to the BARC block 2 and the resist coating block 3. The factory interface block 1 is also useful for transporting processed substrates received from the development processing block 4 to the outside of the track lithography tool. The factory interface block 1 includes a table 712 configured to receive a number of (in the illustrated embodiment, four) cassettes (or carriers) C, and a substrate transfer mechanism 713 for retrieving an unprocessed substrate W from each of the cassettes C and for storing a processed substrate W in each of the cassettes C. The substrate transfer mechanism 713 includes a movable base 714, which is movable in the Y direction (horizontally) along the table 712, and a robot arm 715 mounted on the movable base 714.
The robot arm 715 is configured to support a substrate W in a horizontal position during wafer transfer operations. Additionally, the robot arm 715 is capable of moving in the Z direction (vertically) in relation to the movable base 714, pivoting within a horizontal plane, and translating back and forth in the direction of the pivot radius. Thus, using the substrate transfer mechanism 713, the holding arm 715 is able to gain access to each of the cassettes C, retrieve an unprocessed substrate W out of each cassette C, and store a processed substrate W in each cassette C. The cassettes C may be one or several types including: an SMIF (standard mechanical interface) pod; an OC (open cassette), which exposes stored substrates W to the atmosphere; or a FOUP (front opening unified pod), which stores substrates W in an enclosed or sealed space.
The BARC block 2 is positioned adjacent to the factory interface block 1. Partition 70 may be used to provide an atmospheric seal between the factory interface block 1 and the BARC block 2. The partition 70 is provided with a pair of vertically arranged substrate rest parts 80 and 81 each used as a transfer position when transferring a substrate W between the factory interface block 1 and the BARC block 2.
Referring to
The resist coating block 3 is a processing block for forming a resist film on the substrate W after formation of the AR film in the BARC block 2. In a particular embodiment, a chemically amplified resist is used as the photoresist. The resist coating block 3 includes a resist coating processor 734 used to form the resist film on top of the AR film, a pair of thermal processing towers 732 for performing one or more thermal processes accompanying the resist coating process, and the transport robot 702, which is used to transfer and receive a substrate W to and from the resist coating processor 734 and the pair of thermal processing towers or 732. Each of the coating processing units includes a spin chuck 736, a coating nozzle 738 for applying a resist coating to the substrate W, a spin motor (not shown), a cup (not shown), and the like.
The thermal processing towers 732 include a number of vertically stacked bake chambers and cool chambers. In a particular embodiment, the thermal processing tower closest to the factory interface block 1 includes bake chambers and the thermal processing tower farthest from the factory interface block 1 includes cool chambers. In the embodiment illustrated in
The development processing block 4 is positioned between the resist coating block 3 and the scanner interface block 5. A partition 72 for sealing the development processing block from the atmosphere of the resist coating block 3 is provided. The development processing block 4 includes a development processor 744 for applying a developing solution to a substrate W after exposure in the scanner EXP, a pair of thermal processing towers 741 and 742, and transport robot 703. Each thermal processing chamber 741 and 742 houses a bake plate which is also an electrostatic chuck 745 for holding the substrate W during corresponding thermal processes. For example, the electrostatic chuck 745 is a chuck 20 described in
The interface block 5 is used to transfer a coated substrate W to the scanner EXP and to transfer an exposed substrate to the development processing block 5. The interface block 5 in this illustrated embodiment includes a transport mechanism 754 for transferring and receiving a substrate W to and from the exposure unit EXP, a pair of edge exposure units EEW for exposing the periphery of a coated substrate, and transport robot 704. Substrate rest parts 88 and 89 are provided along with the pair of edge exposure units EEW for transferring substrates to and from the scanner and the development processing unit 4.
The transport mechanism 754 includes a movable base 754A and a holding arm 754B mounted on the movable base 754A. The holding arm 754B is capable of moving vertically, pivoting, and moving back and forth in the direction of the pivot radius relative to the movable base 754A. The send buffer SBF is provided to temporarily store a substrate W prior to the exposure process if the exposure unit EXP is unable to accept the substrate W, and includes a cabinet capable of storing a plurality of substrates W in tiers.
Controller 760 is used to control all of the components and processes performed in the cluster tool, including generating a plurality of instructions for DC power supplies 92, 93, 94 (respectively) to adjust chucking or dechucking voltage pulses applied to the electrostatic chucks 725, 735, or 745 for clamping or declamping substrates on the corresponding bake plates. For example, the instructions include but not limiting to steps described in the method 400. In another example, the instructions may include but not limiting to steps described in the method 600. In yet another example, the controller 760 adjust its control signal by receiving continuous monitor signals about the static charges and gap-distance from one or more capacitance sensors disposed on the electrostatic chuck. The controller 760 is generally adapted to communicate with the scanner EXP, monitor and control aspects of the processes performed in the cluster tool, and is adapted to control all aspects of the complete substrate processing sequence. The controller 760, which is typically a microprocessor-based controller, is configured to receive inputs from a user and/or various sensors in one of the processing chambers and appropriately control the processing chamber components in accordance with the various inputs and software instructions retained in the controller's memory. The controller 760 generally contains memory and a CPU (not shown) which are utilized by the controller to retain various programs, process the programs, and execute the programs when necessary. The memory (not shown) is connected to the CPU, and may be one or more of a readily available memory, such as random access memory (RAM), read only memory (ROM), floppy disk, hard disk, or any other form of digital storage, local or remote. Software instructions and data can be coded and stored within the memory for instructing the CPU. The support circuits (not shown) are also connected to the CPU for supporting the processor in a conventional manner. The support circuits may include cache, power supplies, clock circuits, input/output circuitry, subsystems, and the like all well known in the art. A program (or computer instructions) readable by the controller 760 determines which tasks are performable in the processing chambers. Preferably, the program is software readable by the controller 760 and includes instructions to monitor and control the process based on defined rules and input data.
Additional description of a substrate processing apparatus in accordance with embodiments of the present invention is provided in U.S. Patent Application Publication No. 2006/0245855, entitled “Substrate Processing Apparatus,” the disclosure of which is hereby incorporated by reference in its entirety. Although embodiments of the present invention are described herein in the context of the track lithography tool illustrated in
It is also understood that the examples and embodiments described herein are for illustrative purposes only and that various modifications or changes in light thereof will be suggested to persons skilled in the art and are to be included within the spirit and purview of this application and scope of the appended claims.
