Patent Application
20240003972
The technology of the disclosure relates to automatic test equipment and full functional testing of bare silicon chips.
Recent trends in processor design have been towards disaggregation of the silicon elements that may have formed a system on a chip (SoC) in the past. That is, while a single die may be designed to contain the circuits for high speed I/O, memory controllers, processor cores, and the like, this design is increasingly inefficient. For example, these larger dies are more error prone and eventually reach silicon wafer reticle size constraints. Whether manufactured as a monolithic SoC or as disaggregated chiplets, a manufacturer must then also incur significant costs in manufacturing a chip package to attach before performing quality control assessments.
In conventional quality control assessments, external test equipment performs various interventions via the chip package to test, debug, update, or read various fundamental hardware and firmware elements of the chip. These hardware interventions include automatic test pattern generation (ATPG) scan, memory built-in self-test (BIST), high speed Input/Output (IO) tests and boundary scans for the integrity of the hardware and circuitry via the joint test action group (JTAG) protocol. The hardware and firmware can be debugged and analyzed via various debug ports. Depending on the size and sophistication of the chip, the available hardware access may vary. In many cases regardless of implementation, these testing and debug capabilities cannot perform functions or processes on the chip and can cause manufacturing escapes.
When additional faults are present that are not detected, these faults may then manifest themselves while the computing device is under use by customers. This may result in costly firmware patches, semiconductor redesigns, recalls, RMAs, and other corrections after delivery. Furthermore, for computing devices comprising disaggregated chips in a multi-chip package, a fault on a single chiplet of the package would render the entire package and all chiplets thereon unusable, as the non-faulty chips may not be able to be recovered once packaged. Accordingly, a test method to perform quality control prior to mounting the chip on the package (e.g., a bare silicon test) is needed. Likewise, with the increased complexity of chips and chiplets, more testing than ATPG scan, memory BIST and high speed IO tests are needed to ensure longevity in the field.
The following presents a simplified summary in order to provide a basic understanding of some aspects described herein. This summary is not an extensive overview of the disclosed subject matter. It is intended to neither identify key nor critical elements of the disclosure nor delineate the scope thereof. Its sole purpose is to present some concepts in a simplified form as a prelude to the more detailed description that is presented later.
In an example implementation, a semiconductor die may be tested by attaching a non-packaged semiconductor circuit to a test bed, loading first computer instructions into a memory of the non-packaged semiconductor circuit. The test may operate the non-packaged semiconductor circuit in a test boot mode where the operation includes executing the first computer instructions. The first computer instructions may include one or more skip instructions for skipping one or more operations of installed firmware of the non-packaged semiconductor circuit. The executing of the first computer instructions may include bypassing one or more operations in a boot flow as provided in installed firmware of the non-packaged semiconductor circuit. The first computer instructions may be loaded into the memory via a joint test action group (JTAG) interface after the semiconductor circuit is powered on, the memory being an internal memory of the semiconductor circuit.
In an example implementation, a semiconductor die may include one or more interfaces configured to attach to a test bed, an internal memory, the internal memory being loaded with first computer instructions via the one or more interfaces, and a first processing circuit configured to execute the first computer instructions thereby operating the processing circuit in a test boot mode. The first computer instructions may include one or more skip instructions for skipping one or more operations of installed firmware of the non-packaged semiconductor circuit. The executing of the first computer instructions may include bypassing one or more operations in a boot flow as provided in installed firmware of the non-packaged semiconductor circuit. The first computer instructions may be loaded into the internal memory via a joint test action group (JTAG) interface after the first processing circuit is powered on. The first computer instructions may be executed to perform a functional test of the semiconductor die, the first computer instructions being loaded and executed without the semiconductor die being attached to a die package.
The following description and the annexed drawings set forth in detail certain illustrative aspects of the subject disclosure. These aspects are indicative, however, of but a few of the various ways in which the principles of various disclosed aspects can be employed and the disclosure is intended to include all such aspects and their equivalents. Other advantages and novel features will become apparent from the following detailed description when considered in conjunction with the drawings.
The disclosure herein is described with reference to the drawings, wherein like reference numerals are used to refer to like elements throughout. In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the subject innovation. It may be evident, however, that various disclosed aspects can be practiced without these specific details. In other instances, well-known structures and devices are shown in block diagram form in order to facilitate describing the subject innovation.
The word “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any implementation described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments. Likewise, the term “implementation” does not require that all implementations include the discussed feature, advantage, or mode of operation.
The terminology used herein describes particular implementations only and should not be construed to limit any implementations disclosed herein. As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. Those skilled in the art will further understand that the terms “comprises,” “comprising,” “includes,” and/or “including,” as used herein, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
Various components as described herein may be implemented as application specific integrated circuits (ASICs), programmable gate arrays (e.g., FPGAs), firmware, hardware, software, or a combination thereof. Further, various aspects and/or embodiments may be described in terms of sequences of actions to be performed by, for example, elements of a computing device. Those skilled in the art will recognize that various actions described herein can be performed by specific circuits (e.g., an application specific integrated circuit (ASIC)), by program instructions being executed by one or more processors, or by a combination of both. Additionally, these sequences of actions described herein can be considered to be embodied entirely within any form of non-transitory computer-readable medium having stored thereon a corresponding set of computer instructions that upon execution would cause an associated processor to perform the functionality described herein. Thus, the various aspects described herein may be embodied in a number of different forms, all of which have been contemplated to be within the scope of the claimed subject matter. In addition, for each of the aspects described herein, the corresponding form of any such aspects may be described herein as, for example, “logic configured to”, “instructions that when executed perform”, “computer instructions to” and/or other structural components configured to perform the described action.
Those of skill in the art will further appreciate that the various illustrative logical blocks, components, agents, IPs, modules, circuits, and algorithms described in connection with the aspects disclosed herein may be implemented as electronic hardware, instructions stored in memory or in another computer readable medium and executed by a processor or other processing device, or combinations of both. Memory disclosed herein may be any type and size of memory and may be configured to store any type of information desired. To clearly illustrate this interchangeability, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. How such functionality is implemented depends upon the particular application, design choices, and/or design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present disclosure.
The various illustrative logical blocks, processors, controllers, components, agents, IPs, modules, and circuits described in connection with the aspects disclosed herein may be implemented or performed with a processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).
The aspects disclosed herein may be embodied in hardware and in instructions that are stored in hardware, and may reside, for example, in Random Access Memory (RAM), flash memory, Read Only Memory (ROM), Electrically Programmable ROM (EPROM), Electrically Erasable Programmable ROM (EEPROM), registers, a hard disk, a removable disk, a CD-ROM, or any other form of computer readable medium known in the art. An exemplary storage medium is coupled to the processor such that the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium may be integral to the processor. The processor and the storage medium may reside in an ASIC. The ASIC may reside in a remote station. In the alternative, the processor and the storage medium may reside as discrete components in a remote station, base station, or server.
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The CPU 100 may be configured to connect to other chiplets, such as chiplet 142, chiplet 144, chiplet 146, and chiplet 148 in
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The test bed 220 may include a mount or socket to connect the semiconductor die of the CPU 100 and the SCP 120 to a test environment and various stimuli. The semiconductor die may be attached as in a hardware-in-the-loop arrangement and each pin of the semiconductor die may be driven or monitored by the test bed 220. One or more pins may correspond to power inputs 260 and one or more pins (e.g., four or eight) may correspond to the JTAG ports 170. Likewise, the SCP 120 may connect directly to one or more pins that may be driven to select one or more boot modes. That is, if a first pin is driven, then patching and RMA procedures may be implemented via JTAG 170 and the bootstrap controller 290. If a second pin is driven, the semiconductor die may enter an automatic test equipment (ATE) mode for boot processes. The ATE boot mode may be authenticated by signals transmitted at the second pin or via one or more certificates transmitted over the JTAG ports 170 at power ON.
Various checks, flags, or logic switches may determine early in a boot process, after power ON, which boot mode is to be implemented. These checks may be performed by flags in efuses 211 (e.g., one-time programmable flags) and hardware switches 210. The hardware switches 210 may connect to JTAG ports 170 and receive one or more certificates on boot and the hardware switches 210 may read one or more pins to determine and authorize an appropriate boot mode for the bootstrap controller 290. The bootstrap controller 290 may include firmware that includes instructions for various boot modes. For example, when in an ATE boot mode, the bootstrap controller 290 may execute firmware to generate additional logs, skip various hardware checks (e.g., external hardware checks), or idle to await commands from JTAG 170 before proceeding. This versatile firmware may be hardcoded onto ROM 230 or may be loaded into onboard RAM 240 via JTAG 170 to override hardcoded firmware.
The shared memory 121 may be on-board RAM or secured RAM which can be trusted by the bootstrap controller 290 after an integrity check or certificate check. Indeed, the components of the CPU 100 may be divided into trusted components and non-trusted components, where the trusted components may be verified by certificates, in the case of software components, or are pure hardware components. The RAM 240 may be loaded with executable computer instructions via the JTAG ports 170 which may be read from the RAM 240 to permit the bootstrap controller 290 to perform a different boot process or a reconfigurable boot process. For example, the RAM 240 may be loaded, after initial boot of the bootstrap controller 290, with an Unified Extensible Firmware Interface (UEFI) Basic Input/Output System (BIOS) or a full operating system (e.g., embedded Linux, other small distribution OS, etc.). The initial boot of the bootstrap controller 290 may make the onboard RAM of the CPU 100 or shared memory 121 of the SCP 120 available for loading of instructions via JTAG 170. This onboard RAM or shared memory 121 may then host the BIOS or operating system to be used for functional tests and benchmarks of the CPU 100.
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The firmware on the SCP 120 or bootstrap controller 290 may execute initial computer instructions in accordance with the selected ATE boot mode. That is, the SCP 120 or bootstrap controller 290 may include firmware (e.g., hardcoded ROM) that includes instructions to establish a test boot mode controlled by JTAG 170. Once in an ATE boot mode, the test bed 310 may deliver executable code 321 through the JTAG I/O 320 and SCP 120 into RAM 340 of the SCP 120. In other words, the ATE boot mode will control the SCP 120 to enable the loading of computer instructions into RAM 340 via JTAG I/O 320. The RAM 340 may be onboard RAM located on the SCP 120 or CPU 100 or CPU 350. Since the ATE test is performed on the bare silicon chip, the external components such as the base board management controller (BMC), external memory, and memory controllers may not be connected to the CPU 100/350. In a disaggregated configuration, the CPU 100 may have processor cores and sub-processors and may have few supporting components on-chip.
The executable code 321 may be delivered to RAM 340 by the JTAG 170 interface and once stored may be executed by the SCP 120 or CPU 350, as the case may be. RAM 340 may include SRAM, cache, and other memory onboard various circuits of the CPU 100. The JTAG I/O 320 and related JTAG debug access ports (DAP) may provide computer instructions (e.g., binary or machine language) to perform boot functions not included in the installed firmware (e.g., a UEFI BIOS). The executed boot functions 323 may involve start up or power ON of components of the CPU 350 via the SCP 120 or CPU 350. For example, the executable code 321 may operate to bring the CPU 350 out of reset at operation 331. The executable code 321 may be executed in between steps of the installed firmware. To accomplish this, the ATE boot mode may enable the SCP 120 to halt or fork the boot process based on commands delivered from the JTAG I/O 320. The test bed 310 may monitor the boot process via JTAG I/O 320 and issue halt commands and insert computer instructions into the boot process to branch functionality of the boot process. For example, the SCP 120 may be instructed to skip boot process steps that correspond to power ON of a BMC or memory controller or may be instructed to branch execution to a different set of instructions in RAM 340.
The SCP 120 may also log events in the boot process through operations 325 such that the progression of the boot process and any errors may be monitored by the JTAG I/O 320. These logged events may include circuits brought out of reset, components authenticated, transmission checks, sensor readings, and other functions of the CPU 350 or SCP 120 that have been enabled by the installed firmware or executable code 321. The events may be logged in a buffer of RAM 340 and dumped periodically via the JTAG I/O 320 or via a universal asynchronous receiver/transmitter (UART) interface of the CPU 350. The events may be logged in a cyclical buffer of the JTAG I/O 320 and read out by the test bed 310 periodically or in real time. These events may include errors that are not serious enough to stop function of the boot process but which may nevertheless result in undesirable behavior during normal operations. For example, the JTAG or UART interface may enable the test bed 310 to monitor a normal boot process of installed firmware and identify unexpected events (e.g., buffer overflows, incorrect boot flags, etc.). As noted previously, the hardware-coded boot process may be modified by the executable code 321 to skip steps or instructions that are not possible or could cause unpredictable behavior when executed with the CPU 350 operating as bare silicon without connections to other chiplets or a computing platform. The boot firmware may be configured to automatically skip steps requiring external components (outside the processor under test) and await instructions via JTAG 170 at various points of execution.
After the CPU 350 is brought out of reset and booted to enable execution of instructions, the test bed 310 may deliver executable code 333 to RAM 340. The executable code 333 may be a BIOS or an operating system which may enable further code to be loaded to RAM 340 and executed. As a result, the CPU 350 may be provided with many normal functional execution capabilities despite being in a bare metal silicon form. For example, various functional benchmark tests may be delivered to the RAM 340 as executable code 333 for evaluation of the CPU 350 such as overclocking tests, thermal tests, stress tests, randomized testing, data consistency tests, boundary tests, and other quality control evaluations for the semiconductor circuits. Telemetry data (e.g., power, thermal, and error data) that is normally monitored by external platform entities (e.g., BMC) may be monitored via JTAG access to on-chip sensors.
This execution of processing functions at operation 335 may be monitored to log events in CPU processing at operation 337. Various stimulus tests (e.g., directed and randomized signal tests) 327 can be executed by CPU 350 and the test result(s) can be written to CPU I/O 360 (e.g., CPU pins) or receive inputs from the CPU I/O 360. The test bed 310 may connect to each pin of the bare metal CPU and read the signal tests to verify connectivity on the semiconductor. Likewise, voltage or current margins may be tested via stimulus and recorded by the test bed 310. The logged events in CPU processing at operation 337 may be captured by the test bed 310 via JTAG, UART, a debug communication channel (DCC) or debug access port (DAP), or similar interface with the CPU 350. The processing by the SCP 120 and the CPU 350 may be staged so that executable code 333 is sequentially delivered via JTAG I/O 320 and sequentially executed by the respective processor. In this manner, the functionality of the chiplet or semiconductor circuit may be driven based solely on the JTAG inputs even though the chiplet or semiconductor circuit is not integrated into a package or computing platform.
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Additional executable code 425 may be transmitted via JTAG I/O 320 and SCP 120 to RAM 340. This executable code 425 in RAM 340 may be accessed by the SCP 120 to execute code 434 which may perform various signal tests 435 on the CPU 350. For example, to test various functionality of the CPU and perform ATE tests, the tests' processes may be hosted and executed on the SCP 120 such that the CPU is not brought out of reset. This may simplify initial boot processes. If the CPU 350 is brought out of reset and connected to the SCP 120, then executable code 437 may be transmitted to RAM 340 and such executable code 437 may be accessed by CPU 350 to perform functional tests 450. It is contemplated that further firmware may be extracted as at operation 423 (e.g., from ROM) and further executable code may be transmitted to RAM 340 from JTAG I/O 320 throughout an ongoing ATE testing operation. Logs 442, 444, and 446 may be received from JTAG I/O 320 to identify functional errors, runtime errors, system faults, and other hardware or software errors that may indicate a quality control problem with the chiplet under test.
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The ASIC 500 may be connected to a test bed 310 via I/O interface 510, I/O interface 515, and JTAG interface 530. The test bed 310 may power ON the ASIC 500 and trigger a built-in-test framework of the ASIC 500. The test bed 310 may power ON the ASIC 500 and may stimulate the I/O interface 510 and I/O interface 515 while monitoring the RAM 520 for functional errors or real time errors. The JTAG interface 530 may load computer instructions into RAM 520 where the instructions may be executed by the ASIC 500. For example, errors may be introduced to RAM 520 via JTAG interface 530 to monitor error recovery methods of the ASIC 500. The JTAG interface 530 may have logging capability and a buffer as described previously. The JTAG interface 530 may include a JTAG DAP interface for input and output from RAM 520. The tests of the ASIC 500 may include overclocking tests, thermal tests, stress tests, randomized testing, data consistency tests, boundary tests, and other quality control evaluations for its semiconductor circuits.
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It is also noted that the operational steps described in any of the exemplary aspects herein are described to provide examples and discussion. The operations described may be performed in numerous different sequences other than the illustrated sequences. Furthermore, operations described in a single operational step may actually be performed in a number of different steps. Additionally, one or more operational steps discussed in the exemplary aspects may be combined. It is to be understood that the operational steps illustrated in the flowchart diagrams may be subject to numerous different modifications as will be readily apparent to one of skill in the art. Those of skill in the art will also understand that information and signals may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.
The previous description of the disclosure is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other variations. Thus, the disclosure is not intended to be limited to the examples and designs described herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
