Patent Application
20220404414
The present disclosure generally relates to the wafer testing field, in particular, to a method and a testing apparatus related to wafer testing.
In one of the objectives of the wafer testing, fail bits on the wafer are checked based on one or more testing patterns and conditions, and these fail bits may be fixed through a backup circuit. Regarding the advanced manufacturing process, there may be lots of dies on one wafer, and the memory capacity may also be large, so as to enlarge the data amount of defect analysis. However, a massive data amount may affect the efficiency of defect analysis and new product development. If the defect analysis can be completed during the probe testing, the developer may find out the manufacturing problem of the product and a proper solution as soon as possible.
Taking memory as an example, after probe testing on the wafer of the memory, a testing program may compare the testing result with a previous version and further perform a correction. There would be a need to speed up the development and repeat verification of the testing program.
Accordingly, the present disclosure is directed to a method and a testing apparatus related to wafer testing, to improve the efficiency of defect analysis.
In one of the exemplary embodiments, a method related to wafer testing, includes, but is not limited thereto, the following steps. Testing raw data is obtained by a testing apparatus operating with a Unix-related system. The testing raw data is a testing result of probe testing on one or more wafers by the testing apparatus. The testing raw data is converted into converted data by the testing apparatus. The converted data is related to the defect information of the wafer. Analyzed data is generated by the testing apparatus according to the converted data. The analyzed data is used for a graphical interface.
In one of the exemplary embodiments, a testing apparatus related to wafer testing includes, but is not limited thereto, a memory and a processor. The memory is used for storing program code. The processor is coupled to the memory. The processor is used for loading and executing the program code to be configured for performing the following steps. The processor operates with a Unix-related system, obtains testing raw data, converts the testing raw data into a converted data, and generates analyzed data according to the converted data. The testing raw data is a testing result of probe testing on one or more wafers by the testing apparatus. The converted data is related to the defect information of the wafer. The analyzed data is used for a graphical interface.
It should be understood, however, that this Summary may not contain all of the aspects and embodiments of the present disclosure, is not meant to be limiting or restrictive in any manner, and that the invention as disclosed herein is and will be understood by those of ordinary skill in the art to encompass obvious improvements and modifications thereto.
The accompanying drawings are included to provide a further understanding of the disclosure, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the disclosure and, together with the description, serve to explain the principles of the disclosure.
Reference will now be made in detail to the present preferred embodiments of the disclosure, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts.
The memory 110 may be any type of a fixed or movable random-access memory (RAM), a read-only memory (ROM), a flash memory, a similar device, or a combination of the above devices. In one embodiment, the memory 110 may store program codes, device configurations, buffer data, or permanent data (such as testing data, converted data, or analyzed data), and these data would be introduced later.
The processor 130 is coupled to the memory 110. The processor 130 is configured to load and execute the program code stored in the memory 110, to perform a procedure of the exemplary embodiment of the disclosure.
In some embodiments, the processor 130 may be a central processing unit (CPU), a microprocessor, a microcontroller, a graphics processing unit (GPU), a digital signal processing (DSP) chip, a field-programmable gate array (FPGA). In still some embodiments, the functions of the processor 130 may also be implemented by an independent electronic device or an integrated circuit (IC), and operations of the processor 130 may also be implemented by software.
In one embodiment, the processor 130 operates with a Unix-related system. The Unix-related system could be Unix or Linux operating system (OS) and may be different from the Windows OS. For example, the Linux OS could be SuSE or CentOS. One or more testing programs are executed on the Unix-related system. For example, a testing program generates testing patterns for the wafer.
In some embodiments, the testing apparatus 100 further includes a communication transceiver 150 coupled to the processor 130. The communication transceiver 150 could be a serial peripheral interface (SPI), an inter-integrated circuit (I2C), a universal asynchronous receiver transmitter (UART), or another physical interface. Alternatively, the communication transceiver 150 could be Wi-Fi, Bluetooth, or mobile network supported transceiver. In one embodiment, the communication transceiver 150 is used to communicate with an external apparatus (such as a computer or a smartphone). For example, a developer may use a computer to log in to the Unix-related system operated on the testing apparatus 100.
To better understand the operating process provided in one or more embodiments of the disclosure, several embodiments will be exemplified below to elaborate the testing apparatus 100. The devices and modules in the testing apparatus 100 are applied in the following embodiments to explain the method related to multiple modes provided herein. Each step of the method can be adjusted according to actual implementation situations and should not be limited to what is described herein.
For example, a memory test, which provides address sequences and test data sequences related to one or more testing patterns to the memory, is performed by testing circuitry of the testing apparatus 100, and the test results are recorded in the memory 110 for being accessed by, or transmission to, the processor 130. In one embodiment, all tests to be done on the memory block are performed first, and complete test results are provided to the processor 130 at the beginning of the method. In another embodiment, tests to be done are performed concurrently with, or in response to, one or more operations in the method.
The processor 130 may convert the testing raw data into converted data (step S230). Specifically, the testing raw data is configured with a specific file format based on the testing program. For example, the Advantest program is configured with Advantest language (ATL). For subsequent defect analysis, a file conversion would be performed on the testing raw data, to generate the converted data. The converted data is readable by the Unix-related system operated on the testing apparatus 100. The converted data is related to defect information of one or more wafers.
In one embodiment, the converted data includes one or more defect locations of the wafer. The defect location is the address of the fail/error sub-unit. It should be noticed that, regarding the wafer of memory, the defect information is configured with multiple column lines and multiple row lines. A crossing region of one column line and one row line is a sub-unit of one wafer. The sub-unit could be a memory cell/block, a bit, a die, a chip, or another unit based on the actual requirement.
In one embodiment, the converted data includes one or more DC values of the sub-units of the wafer. In one embodiment, the converted data includes the bin identifications of the sub-units of the wafer. For example, bin value of 1 for a good bin, and bin 10 for an open circuit. In one embodiment, the converted data includes the identifier of the wafer, Lot (i.e., a set of wafers), and/or chip.
The processor 130 may generate analyzed data according to the converted data (step S250). Specifically, the analyzed data is used for a graphical interface. The graphical interface may be developed by XView or another window system application. The graphical interface would be displayed on a display. In one embodiment, the display could be embedded in or externally connected with testing apparatus 100. In another embodiment, an external apparatus may log in to the testing apparatus 100 through remote control, and the graphical interface may be displayed on the display of the external apparatus.
In one embodiment, the analyzed data may include an information map. The information map shows the defect information at a global view of the wafer. The processor 130 may generate the information map configured with the column lines and the row lines.
In one embodiment, the information map is a fail region latch (FRL) map.
In one embodiment, the processor 130 may overlap the FRL maps of multiple wafers based on corresponding column lines and corresponding row lines. Hence, the one column line of one map would be aligned with the same column line of another map, and one row line of one map would be aligned with the same row line of another map.
In some embodiments, in response to a selection of multiple reference specs, the processor 130 may configure different visual appearances for different reference specs. For example, a first fail region is determined by comparing with a first reference spec and configured with a third color, and a second fail region is determined by comparing with a second reference spec and configured with a fourth color.
In one embodiment, the processor 130 may count the number of sub-units corresponding to one or more classified items. The classified items are related to defect location, testing pattern, or DC value. The processor 130 may generate an accumulated chart according to a second counted result of the classified items. The second counted result includes the number of sub-units corresponding to the classified items.
In one embodiment, the accumulated chart is a fail address distribution. For example,
In one embodiment, the accumulated chart is a fail region count (FRC). For example,
In one embodiment, the information map is a bin map.
In one embodiment, the information map is a DC map. A DC value would be shown on the location of each die/chip.
In some embodiments, the information map could be another measured value map. The measured value may be related to voltage, current, impedance, or another electrical characteristic. A measured value would be shown on the location of each die/chip.
In one embodiment, the accumulated chart is a DC distribution. For example,
In some embodiments, the processor 130 may compare the test time of each test item or each testing pattern.
In summary, according to the method and the testing apparatus related to wafer testing, in response to obtaining the testing result of the probe testing, the testing apparatus operating with Unix-related system may directly convert the testing raw data and further generate analyzed data used for being presented on the graphical interface. Compared with conventional Windows OS-based defect analysis, the defect analysis may be performed on the testing apparatus directly, so as to provide real-time defect analysis.
It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present disclosure without departing from the scope or spirit of the disclosure. In view of the foregoing, it is intended that the present disclosure cover modifications and variations of this disclosure provided they fall within the scope of the following claims and their equivalents.
