CROSS REFERENCE TO RELATED APPLICATIONS
This Application claims priority to Taiwan Patent Application No. 092121411 filed Aug. 5, 2003.
FIELD OF THE INVENTION
The present invention provides a method for avoiding short circuits of conductive wires, and more particularly, of conductive wires in semiconductor processes.
BACKGROUND OF THE INVENTION
With the growth of industrial technology, the dimension of semiconductor process gets smaller and smaller to satisfy the requirement of more and more complex ultra large-scale integration. The problem coming along with smaller critical dimension is that short-circuits among wires happen more easily, and the problem seriously affects the yield and the reliability of the integration. Especially in the complex integration, the wires and contacts made by etching and deposition (for example, bit-line contacts) have short-circuit problems due to minor difference occurring while having the insufficient process window during the process.
FIG. 1 shows a top view of the wires and bit-line contacts of prior art. FIG. 1 shows the relative location of a gate 103, a wire 105 and a bit-line contact 101. The profile of I-I′ section is shown in FIG. 2. FIG. 2 shows a profile of the wires and bit-line contacts of prior art. In FIG. 2, on the semiconductor substrate 201 is an insulation layer 203, which has a predetermined opening and the conductive layer is in the opening. As shown in FIG. 2, there are the wires 105 on the conductive layer 205 and the insulation layer 203 after the metallic deposition. The short-circuit problem happens after the wire 105 deposition if an improper etching process generates an over-scale trench (Illustrated in FIG. 2).
SUMMARY OF THE INVENTION
The present invention provides a method for avoiding short circuits of conductive wires. The method of the present invention includes a spacer process to avoid contact between the wires and the bit-line contact to increase the yield.
The present invention provides a method for avoiding short circuits of conductive wires, and more particularly, for avoiding short-circuit of bit-line contacts and the wires in semiconductor process.
The methods of the present invention are described as follows. A substrate having a contact area is provided. A first opening is formed in the substrate to expose the contact area. The first opening is filled with a first conductive material to form a first conductive layer. A portion of the first conductive layer is removed to form a second opening for exposing a sidewall of the substrate. A spacer is formed on the sidewall. The second opening is filled with a second conductive material to form a second conductive layer. A patterned dielectric layer is formed over the substrate. The patterned dielectric layer defines a wire opening to expose the second conductive layer. The wire opening is filled with a third conductive material to form a wire electrically contacting the second conductive layer.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 shows a top view of the wires and bit-line contacts of the prior art.
FIG. 2 shows a profile of the wires and bit-line contacts of the prior art.
FIG. 3
a shows a profile of the embodiment of the present invention.
FIG. 3
b shows a profile of the embodiment of the present invention.
FIG. 3
c shows a profile of the embodiment of the present invention.
FIG. 3
d shows a profile of the embodiment of the present invention.
FIG. 3
e shows a profile of the embodiment of the present invention.
FIG. 3
f shows a profile of the embodiment of the present invention.
FIG. 3
g shows a profile of the embodiment of the present invention.
FIG. 3
h shows a profile of the embodiment of the present invention.
FIG. 3
i shows a profile of the embodiment of the present invention.
DETAILED DESCRIPTION OF THE INVENTION
The present invention provides a method for avoiding short circuits of conductive wires. The preferred embodiment of the present invention is the wires of the semiconductor component, for example, the wires and bit-line contacts of dynamic random access memory. Besides, the method can be applied to other processes to solve the short-circuit problem.
FIG. 3
a shows a profile of the embodiment of the present invention. A substrate 300 includes a semiconductor substrate 301 having a contact area 33 and an insulation layer 303 on it. The substrate 300 is provided for the manufacture of the integration components.
FIGS. 3
b-3e show profiles of the embodiment of the present invention, and the order of the Figs follows the process sequence. As FIG. 3b shows, a first opening 31 is formed at the insulation layer 303 of the substrate 300 to expose the contact area 33. The contact area 33 could be a bit-line contact area. The mentioned opening can be formed by photolithography and etching. The first opening 31 is used for deposition of conductive layer follow up, and the disposition is determined by the design. The steps forming the first opening 31 includes: forming a patterned photoresist layer on the insulation layer 303, the patterned photoresist layer defining the first opening 31; using the photoresist layer as a mask to etch the insulation layer 303 to expose the bit-line contact area 33.
As FIG. 3c shows, filling the first opening 31 with a first conductive material to form a first conductive layer 305 electrically connecting to the contact area 33. The first conductive material could be poly-silicon or other similar substances. The steps forming the first conductive layer 305 include: depositing a poly-silicon layer over the substrate 300 and filling the first opening 31.
Then, as FIG. 3d shows, removing a portion of the first conductive layer 305 to form a second opening 32 for exposing a sidewall 34 of the substrate 300. The way to form the second opening 32 could be etching back the first conductive layer 305 to expose the sidewall 34 of the substrate 300.
As FIG. 3e shows, a spacer 307 is formed on the sidewall 34. The spacer 307 could be made of nitride oxide or other similar substances. The steps forming the spacer 307 include: forming a conformal dielectric layer over the substrate 300, and anisotropically etching the conformal dielectric layer to form the spacer 307 on the sidewall 34.
As FIG. 3f shows, the second opening 32 is filled with a second conductive material to form a second conductive layer 309. The second conductive material could be poly-silicon or other similar substances. The steps forming the second conductive layer 309 include: depositing a poly-silicon layer over the substrate 300, filling the second opening 32 with the poly-silicon layer, and etching back the poly-silicon layer to expose a portion of the spacer 307.
As FIG. 3g shows, forming a dielectric layer 313 over the substrate 300 and the second conductive layer 309, and forming a patterned photoresist 317 on the dielectric layer 313.
As FIG. 3h shows, the patterned photoresist 317 defines a wire opening 319. The pattern photoresist 317 is used as a mask and the dielectric layer 313 is etched corresponding to the second conductive layer 309 to expose the second conductive layer 309. In other wires positions not contacting the bit-line contact, the dielectric layer 313 and a portion of the insulation layer 303 are also etched. The patterned photoresist 317 is removed to form the patterned dielectric layer 313. In the mentioned method, we can planarize the dielectric layer 313 by the chemical-mechanical polishing method before the patterned photoresist 317 is formed.
As FIG. 3i shows, the wire opening 319 is filled with a third conductive material to form the wires 311 and 315. The wire 311 electrically contacts the second conductive layer 309 and the number of the wires 311 can be designed to satisfy users' demands. The third conductive material can be wolfram or other similar metals. The steps forming the wire include: forming a metallic layer over the patterned dielectric layer 313, filling the wire opening 319, and planarizing the metallic layer to form the wires 311 and 315.
As shown in FIG. 3i, the first conductive layer 305 is electrically connected to the second conductive layer 309 in this embodiment and together they form a bit-line contact. The spacer 307 of the present invention can increase the distance between the wire 315 and the bit-line contact to avoid short circuits effectively.
While the invention has been described in connection with what is presently considered to be the most practical and preferred embodiments, it is to be understood that the invention is not to be limited to the discovered embodiments. The invention is intended to cover various modifications and equivalent arrangement included within the spirit and scope of the appended claims.
Patent Application
20050032343
