Claims
- 1. An SOI semiconductor device including a substrate defining a surface and having a buried oxide layer spaced from the surface and plural component isolation regions extending vertically from the surface to below the buried oxide layer formed in the substrate, the isolation regions including Silicon and at least one of Oxygen, and Nitrogen.
- 2. The device of claim 1, wherein the isolation regions include Silicon, Oxygen, and Nitrogen.
- 3. The SOI device of claim 2, wherein the substrate defines a surface and the device includes a buried oxide layer, and the isolation regions are formed by implantation of oxygen into the substrate and extend from the surface to below the buried oxide layer.
- 4. The device of claim 1 wherein the Oxygen and/or Nitrogen have/has a uniform concentration.
- 5. An SOI semiconductor device including a substrate defining a surface and having a buried oxide layer spaced from the surface and plural component isolation regions extending vertically from the surface to below the buried oxide layer, the isolation regions formed in situ in the substrate, the isolation regions including Silicon and at least one of: Oxygen, and Nitrogen.
- 6. The device of claim 5 wherein the isolation regions include Silicon, Oxygen and Nitrogen.
- 7. The device of claim 5 wherein the Oxygen and/or Nitrogen have/has a uniform concentration.
- 8. An SOI semiconductor device including a substrate defining a surface and having a buried oxide layer spaced from the surface and at least one component isolation region extending from the surface to below the buried oxide layer formed in the substrate, the isolation region including Silicon and at least one of Oxygen, and Nitrogen.
- 9. The device of claim 8 wherein the isolation regions include Silicon, Oxygen and Nitrogen.
- 10. The device of claim 8 wherein the Oxygen and/or Nitrogen have/has a uniform concentration.
Parent Case Info
This is a divisional patent application of application Ser. No. 09/479,493, filed Jan. 7, 2000. This application claims the benefit of U.S. Provisional Application for patent application Ser. No. 60/169,695, filed on Dec. 7, 1999 and entitled METHOD FOR ESTABLISHING COMPONENT ISOLATION REGIONS IN SOI SEMICONDUCTOR DEVICE.
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Date |
Kind |
4922318 |
Thomas et al. |
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A |
6204532 |
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Foreign Referenced Citations (1)
Number |
Date |
Country |
11-284146 |
Oct 1999 |
JP |
Provisional Applications (1)
|
Number |
Date |
Country |
|
60/169695 |
Dec 1999 |
US |