METHOD FOR FABRICATING A SEMICONDUCTOR DEVICE

Abstract

An embodiment of the invention provides a method for forming a semiconductor device comprising providing a substrate with a pad layer formed thereon. The pad layer and the substrate are patterned to form a plurality of trenches. A trench top insulating layer is formed in each trench. Wherein the trench top insulating layer protrudes from the substrate and has an extension portion extending to the pad layer. The pad layer and the substrate are etched by using the trench top insulating layers and the extension portions as a mask to form a recess in the substrate. And a recess gate is formed in the recess.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention can be more fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein:

FIGS. 1-7 are schematic views showing an exemplary embodiment of a method for forming a memory with a recessed vertical transistor.

Claims

1. A method for forming a semiconductor device, comprising: providing a substrate with a pad layer formed thereon;patterning the pad layer and the substrate to form a plurality of trenches;forming a trench top insulating layer in each trench, wherein the trench top insulating layer protrudes from the substrate and has an extension portion extending to the pad layer;etching the pad layer and the substrate by using the trench top insulating layers and the extension portions as a mask to form a recess in the substrate; andforming a recess gate in the recess.

2. The method for forming a semiconductor device as claimed in claim 1, further comprising forming a trench capacitor in each trench and below each trench top insulating layer.

3. The method for forming a semiconductor device as claimed in claim 1, wherein the step of etching the pad layer and the substrate by using the trench top insulating layers and the extension portions as a mask to form a recess in the substrate comprises: etching the pad layer by using the trench top insulating layers and the extension portions as a mask while leaving the pad layer underlying the extension portions, thus to form an opening, which is surrounded by spacers, on the substrate; andetching the substrate in the opening by using the trench top insulating layer, the extension portions and the spacers as a mask.

4. The method for forming a semiconductor device as claimed in claim 1, further comprising implanting the substrate to form a source and a drain region on opposite sides of the recess gate.

5. The method for forming a semiconductor device as claimed in claim 1, wherein the pad layer comprises a pad oxide and a pad nitride.

6. The method for forming a semiconductor device as claimed in claim 1, wherein forming the trench top insulating layer in each trench comprises performing a high density plasma chemical vapor deposition.

7. The method for high density plasma chemical vapor deposition as claimed in claim 6, wherein the deposition/sputtering a ratio of about 3 to 4.

8. The method for forming a semiconductor device as claimed in claim 6, wherein performing the high density plasma etching comprises a process wherein the trench top insulating layer is deposited in the trench and protrudes from the substrate, and the pad layer adjacent to corners of the trench is etched away.

9. The method for forming a semiconductor device as claimed in claim 1, wherein the trench top insulating layer comprises silicon oxide.

10. The method for forming a semiconductor device as claimed in claim 3, wherein the spacers comprise straight profile sidewalls.

11. The method for forming a semiconductor device as claimed in claim 1, further comprising performing a planarization process after forming the trench top insulating layer.

12. The method for forming a semiconductor device as claimed in claim 11, wherein thickness of the trench top insulating layer protruding from the substrate is 1.5 times as wide as a minimum line width of the recess gate.

13. The method for forming a semiconductor device as claimed in claim 3, wherein the step of forming the recess gate in the recess comprises: forming a gate dielectric layer on sidewalls and bottom of the recess;filling a layer of conductive material in the recess; andpolishing the layer of conductive material, the spacer and the trench top insulating layer to form the recess gate.

14. The method for forming a semiconductor device as claimed in claim 3, wherein after forming the opening on the substrate, thickness of the trench top insulating layer above the substrate is substantially larger than a minimum line width of the recess gate.

15. A semiconductor device structure, comprising: a substrate having a plurality of trenches therein;a trench top insulating layer in each trench and protruding from the substrate, wherein the trench top insulating layer comprises an extension portion wider than the trench;spacers disposed on sidewalls of the trench top insulating layers and underlying the extension portions;a recess within the substrate between the spacers of neighboring trenches; anda recess gate in the recess.

16. The semiconductor device structure as claimed in claim 15, wherein the trench top insulating layer and its extension portion are formed by a high density plasma chemical vapor deposition having a deposition/sputtering ratio of about 3 to 4.

17. The semiconductor device structure as claimed in claim 15, wherein the trench top insulating layer comprises silicon nitride.

18. The semiconductor device structure as claimed in claim 15, wherein thickness of the spacer is substantially greater than a minimum line width of the recess gate.

19. The method for forming a semiconductor device as claimed in claim 15, wherein the recess gate protrudes from the substrate.

20. The semiconductor device structure as claimed in claim 15, wherein the recess gate comprises: a gate dielectric layer formed on sidewalls and bottom of the recess; anda layer of conductive material in the recess.