This application claims priority to German Patent Application 10 2005 042 071.0-33, which was filed Aug. 31, 2005 and is incorporated herein by reference.
The invention relates to a method for fabricating a semiconductor structure having a transistor cell region (or cell array), in which transistors are arranged closely adjacent alongside one another, and having a connection region, in which transistors are at a greater distance from one another than in the transistor cell region.
Semiconductor structures of this type are used for example in the fabrication of memory cells such as DRAM memory cells. The transistor cell region, in which the transistors are arranged closely adjacent alongside one another forms the actual memory region in said memory cells. The memory region also contains capacitors in addition to the transistors, which capacitors are connected to the transistors and in which capacitors the items of information to be stored are stored in the form of electrical charges. The connection region of such a memory cell is to be differentiated from the memory region; in the connection region, the transistors are at a greater distance from one another than in the transistor cell region. Different transistors, for example, transistors that have a higher electrical loading capacity or are faster, than in the transistor cell region are usually used in the connection region.
In one aspect, the invention specifies a method that enables a simple and readily reproducible fabrication of spacers on or at the transistors of the aforementioned connection region.
The term “spacers” that is customary in the jargon, is to be understood to mean layers which run perpendicular, at least substantially perpendicular, to the surface of the substrate and define a lateral spacing. By way of example, the spacers on the side edges of an elevated structure may serve as an implantation mask and ensure that, during an implantation, the implantation substances directed onto the substrate cannot penetrate onto regions of the substrate whose width is defined by the spacers. Spacers may also serve for electrical insulation.
Accordingly, embodiments of the invention provide for the transistors both of the transistor cell region and of the connection region to be coated with a first, preferably conformal oxide layer. The layer thickness of said first oxide layer is dimensioned in such a way that a gap region in each case remains present between adjacent transistors in the transistor cell region. A sacrificial structure is subsequently applied in the gap region between at least two adjacent transistors of the transistor cell region, at least one gap region in each case remaining free, that is to say without a sacrificial structure, between two adjacent sacrificial structures. A second, preferably conformal, oxide layer is then applied to the sacrificial structures and to the first oxide layer. The first and second oxide layers are then subjected to an etching step in which a spacer having a predetermined spacer width is formed on the side edges of at least one transistor of the connection region. The spacer is formed by the first and second oxide layers and the spacer width is determined by the layer thickness of the first and second oxide layers and also by the etching step.
One advantage of a preferred embodiment of the invention can be seen in the fact that an oxide layer is deposited on the sacrificial structures. An oxide layer can be removed from the sacrificial structures during the further processing, for example, during a subsequent CMP (chemical mechanical polishing) step, significantly better than other material layers such as, by way of example, a silicon nitride layer.
Another advantage of some embodiments of the invention can be seen in the fact that the spacer width can be set very accurately and reproducibly because the spacers are exclusively formed by layers of one and the same material in the case of the invention. Consequently, it is possible to effect significantly better control during spacer fabrication, in particular during spacer etching, and during the setting of the spacer width than is the case with spacers that comprise two different materials such as an oxide as first layer and a nitride as second layer.
Field effect transistors are preferably fabricated as transistors. In this case, the spacers are preferably formed in each case on the side edges of the gate contact of the transistors of the connection region.
It can be regarded as advantageous, moreover, if the second oxide layer is deposited with a layer thickness such that the gap regions without a sacrificial structure in the transistor cell region are completely filled with oxide material. The advantage of this measure is that prior to carrying out the etching step for forming the spacers, it is not necessary to cover the gap regions beforehand—for example, with an etching protective layer (e.g., resist layer)—this is because the second oxide layer alone is already sufficient for covering the gap regions.
An anisotropic etching method is preferably used for fabricating the spacers. If the width of the spacers is subsequently intended to be additionally “readjusted” then it is possible, by way of example, to carry out a second etching step with a lateral etching rate or with an isotropic etching behavior and thus subsequently reduce the width of the spacers.
As an alternative, for fabricating the spacers it is also possible to use an etching method which, although it is essentially anisotropic, also affects slight etching in a lateral direction and, consequently, has at least also an “isotropic” behavior. With the use of such an etching method, the resulting spacer width can already be reduced during etching, so that a desired spacer width can still be set very accurately even if one of the two or else both oxide layers had originally been applied thicker than necessary.
Material fabricated with TEOS (tetraethyl orthosilicate) has particularly good properties for spacers so that it is regarded as advantageous if a TEOS layer is deposited as a first and/or second oxide layer. TEOS material is preferably used for both layers.
A multilayer contact is preferably fabricated as gate contact, in order to achieve optimum contact properties. By way of example, the multilayer contact is formed by a polysilicon layer and an overlying metal or metal silicide layer.
The sacrificial structures are preferably removed after spacer fabrication, for example after carrying out a CMP step. Afterward, a transistor contact for at least one of the two spatially assigned transistors is preferably fabricated in each case in the cavities that arise as a result in the place of the sacrificial structures. By way of example, the transistor contacts are formed on a source or drain zone of the respective transistor.
The spacers may serve, for example as a mask for an implantation step in which highly doped contact regions are formed within the source and drain regions of the transistors of the connection region. The highly doped contact regions are thus at a distance from one another determined by the width of the spacers.
In order to form memory cells, capacitors are also preferably fabricated in the region of the transistor cell region. The capacitors, together with the transistors of the transistor cell region, form memory cells, in particular DRAM memory cells. By way of example, trench or deep trench capacitors may be fabricated as capacitors, but other types of capacitors can also be used.
Moreover, the method described can also be used in the production of analog or digital logic components or in the production of processors, to be precise irrespective of whether field effect transistors or bipolar transistors are used.
The invention is explained in more detail below by way of example, on the basis of exemplary embodiments. In the figures:
FIGS. 1 to 10 show a first exemplary embodiment of the method according to the invention, in which the gap region between transistors of the transistor cell region is covered by an additional protective layer during the fabrication of the spacers in the connection region; and
The following list of reference symbols can be used in conjunction with the figures:
Gate contacts 80 of the two n-channel field effect transistors 40 and 50 are in each case constructed in two layers and are in each case formed by a polysilicon layer 90 and an overlying tungsten or tungsten nitride layer 100. A silicon nitride covering 110 covers the two gate contacts 80 at the top. The lower part of the gate contacts 80 is covered by a further, for example, thermal oxide layer 120.
After the deposition of the first oxide layer 210, a polysilicon layer 220 is deposited on the semiconductor substrate 10 over the whole area. The resulting structure is shown in
Since the thickness of the polysilicon layer 220 may differ slightly in the transistor cell region 20 and in the connection region 30 on account of the structure differences, a CMP step can subsequently be carried out to achieve a uniform thickness of the polysilicon layer 220 over the semiconductor substrate 10.
A silicon nitride hard mask 230, comprising a silicon nitride layer 240 and, if appropriate, an intermediate layer 250, and a photoresist layer 260 is subsequently deposited onto the polysilicon layer 220. The photoresist layer 260 has already been patterned in the illustration in accordance with
The polysilicon layer 220 is subsequently subjected to an etching step during which the polysilicon is completely removed outside the mask section 270. A sacrificial structure 300 remains under the mask section 270, and may be used for example in a later process stage for forming a transistor contact for at least one of the two transistors 40 and/or 50. The sacrificial structure 300 thus forms as if it were a type of place marker for the later transistor contact.
As can additionally be discerned in
In the sectional plane of the semiconductor substrate 210 as shown in
In a subsequent process step, the semiconductor structure in the transistor cell region 20 is covered with a protective layer 400, for example, a photoresist protective layer. The connection region 30 remains uncovered, so that, in an etching step, which is preferably completely or at least largely anisotropic, with the two oxide layers 210 and 330, spacers 410 and 420 are formed on the side edges 425 of the gate contacts 80 of the transistor 200. The width of the spacers 410 and 420 may—if desired—subsequently be reduced by means of a laterally etching etchant and be brought to a desired dimension. The photoresist protective layer 400 is used, during the etching of the spacers, to preserve the bottom region 430 of the gap regions 350 against “etching free” or complete removal of the oxide protective layer formed by the two oxide layers 210 and 330 and to protect the substrate.
Irrespective of whether the spacers are formed with a photoresist protective layer 400 according to the variant in accordance with
The spacers (400, 410) may be used as a mask for an implantation step during which highly doped contact regions are formed within the source and drain region of the transistors (200) of the connection region (30).
Capacitors can also be fabricated in the region of the transistor cell region (30), said capacitors, together with the transistors (40, 50, 340, 360) of the transistor cell region, forming memory cells, in particular DRAM memory cells.
Number | Date | Country | Kind |
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102005042071.0-33 | Aug 2005 | DE | national |