Claims
- 1. A method for fabricating a semiconductor device, the method comprising the steps of:
- sequentially forming a pad oxide film, a first polysilicon film, a silicon oxide film, a nitride film and a second polysilicon film, on a silicon substrate;
- defining active and inactive regions by using a trench mask and forming a trench at both sides of the active region by etching;
- depositing an insulating material in the trench and on the remaining portion of the second polysilicon film such that the trench is filled to form an insulating film for isolating;
- polishing the insulating film using the remaining portion of the second polysilicon film as a first polishing stopper;
- removing the remaining portion of the second polysilicon film and polishing the insulating film using the remaining portion of the nitride film as a second polishing stopper;
- removing the remaining portion of the nitride film and the remaining portion of the silicon oxide film;
- depositing and patterning a protective insulating film such that it remains only on the active region;
- removing the resulting exposed portion of the remaining portion of the first polysilicon film to expose a surface of the pad oxide film;
- performing a thermal oxidation to form a field oxide film only at the inactive region; and
- removing the films formed on the pad oxide film of the active region.
- 2. The method as defined in claim 1, wherein the depth of the trench is set in the range of 5 .mu.m or less, and the width of the trench is set at 3 .mu.m or less.
- 3. The method as defined in claim 1, wherein the first polysilicon film has a thickness of about 2000 .ANG. and the pad oxide film has a thickness of from 300 .ANG. to 500 .ANG..
- 4. The method as defined in claim 1, wherein the insulating material filled in the trench is formed of one of BPSG, silicon nitride and polyimide.
Priority Claims (1)
Number |
Date |
Country |
Kind |
94-30990 |
Nov 1994 |
KRX |
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Parent Case Info
This is a division of application Ser. No. 08/354,868 filed Dec. 19, 1994, now abandoned.
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Non-Patent Literature Citations (1)
Entry |
Shimizu, N., et al, "A Poly Buffered LOCOS Process for 256 Mbit DRAM Cells", IEDM '92, pp. 279-282. |
Divisions (1)
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Number |
Date |
Country |
Parent |
354868 |
Dec 1994 |
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