This application claims the priority benefit of Taiwan application serial no. 103135650, filed on Oct. 15, 2014. The entirety of the above-mentioned patent application is hereby incorporated by reference herein and made a part of this specification.
1. Field of the Invention
The invention relates to a method for fabricating a semiconductor device.
2. Description of Related Art
As the size of the semiconductor device continues to be smaller, the integration of different devices on the same chip has become the trend in the design and the fabrication of a product. Using a non-volatile memory as example, a memory cell, a low-voltage device, a high-voltage device, or a capacitor . . . etc. are, for instance, included on the same chip at the same time. The devices in the substrate are, for instance, isolated by shallow-trench isolation (STI) structures, and respectively include a gate and a gate oxide layer. Since the needed operation voltage and the efficacy of different devices are different, the thicknesses of the gate oxide layers are also different.
In general, a method for fabricating gate oxide layers having different thicknesses includes disposing isolation structures in the substrate to define active areas, and then forming gate oxide layers having different thicknesses in different active areas. However, in the fabrication process, when gate oxide layers having other thicknesses are removed, a divot is formed in the peripheral portion of a top corner of the active areas. Moreover, as the number of times the gate oxide layers are removed is increased, the generated divot region also becomes larger. For instance, the divot region of a low-voltage device region is often greater than the divot region of a high-voltage device region. Since the thickness of the gate oxide layer of the divot region is smaller, the gate oxide layer readily becomes the path of leakage current of the device. As a result, electrical issues such as breakdown voltage or starting voltage are generated, such that the reliability of the device is reduced.
Therefore, how to solve the issue of the generation of a divot in the periphery of a top corner of the active areas when gate oxide layers having different thicknesses are fabricated, so as to prevent the generation of leakage current of a device and thereby increase the reliability of the device, is a current topic that needs to be researched.
The invention provides a method for fabricating a semiconductor device. The method can alleviate the issue of the generation of a divot in the periphery of a top corner of an active area so as to prevent the generation of leakage current of a device, and thereby increase the reliability of the device.
The invention provides a method for fabricating a semiconductor device including the following steps. A substrate is provided. The substrate includes a memory cell region and a peripheral region, and a plurality of isolation structures are formed in the substrate. Each of the isolation structures contains an exposed portion protruding beyond the surface of the substrate. A first dielectric layer is formed on the substrate. A protective layer is formed on a sidewall of the exposed portion of each of the isolation structures. The first dielectric layer on the peripheral region is removed. A second dielectric layer is formed on the substrate of the peripheral region.
In an embodiment of the invention, the protective layer is formed by the following steps. A material layer is formed on the substrate to cover the first dielectric layer and the isolation structures. The material layer covering the first dielectric layer and a portion of the isolation structures is removed to form a protective layer on a sidewall of the exposed portion of each of the isolation structures.
In an embodiment of the invention, the material layer is formed by performing an etch-back process.
In an embodiment of the invention, the protective layer is formed by performing a chemical vapor deposition process.
In an embodiment of the invention, the material of the protective layer includes α-Si, SiO2, SiN, or a combination thereof.
In an embodiment of the invention, the thickness of the protective layer is between 3 nm and 10 nm.
In an embodiment of the invention, the thickness of the protective layer after the second dielectric layer is formed is greater than the thickness of the protective layer before the second dielectric layer is formed.
In an embodiment of the invention, the first dielectric layer is removed by performing a wet etching process.
In an embodiment of the invention, the peripheral region includes a first region and a second region. Moreover, after the step in which the second dielectric layer is formed on the substrate of the peripheral region, the following steps are included. The second dielectric layer on the second region is removed. A third dielectric layer is formed on the substrate of the second region, wherein the thickness of the third dielectric layer is less than the thickness of the second dielectric layer.
In an embodiment of the invention, the second dielectric layer is removed by performing a wet etching process.
In an embodiment of the invention, the peripheral region further includes a third region. Moreover, after the step in which the third dielectric layer is formed on the substrate of the second region, a step in which a fourth dielectric layer is formed on the substrate of the third region is further included.
In an embodiment of the invention, the thickness of the fourth dielectric layer is less than the thickness of the third dielectric layer.
In an embodiment of the invention, the thickness of the fourth dielectric layer is less than the thickness of the third dielectric layer.
In an embodiment of the invention, the first region is a medium-voltage device region, and the second region and the third region are low-voltage device regions.
In an embodiment of the invention, the second region is used to form an input/output transistor, and the third region is used to form a core transistor.
In an embodiment of the invention, the isolation structures are formed by the following steps. A liner layer and a mask layer are formed on a substrate. The mask layer, the liner layer, and the substrate are patterned to form a plurality of trenches in the substrate. An insulation material layer is filled in the trenches. The liner layer and the mask layer are removed to form the isolation structures.
In an embodiment of the invention, the thickness of the second dielectric layer is between 150 angstroms and 200 angstroms.
Based on the above, in the method for fabricating a semiconductor device of the invention, by disposing a protective layer on a sidewall of an isolation structure, the protective layer can prevent the isolation structure adjacent to the periphery of a top corner of an active area from being removed when a dielectric layer on the active area is removed, thereby preventing the generation of a divot in the periphery of a top corner of the active area. Moreover, since the protective layer is located on a sidewall of the isolation structure protruding beyond the surface of the substrate, side etching to the isolation structure caused by an etchant can be prevented, and therefore the generation of a divot in the periphery of a top corner of the active area is prevented. As a result, electrical issues such as leakage current of a device are prevented, and the reliability of the device is thus increased.
In order to make the aforementioned features and advantages of the disclosure more comprehensible, embodiments accompanied with figures are described in detail below.
The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.
Referring to
Then, a liner layer 12 is formed on the substrate 10. The material of the liner layer 12 is, for instance, silicon oxide. The liner layer 12 is formed by performing, for instance, a thermal oxidation process. Then, a mask layer 14 is formed on the liner layer 12. The material of the mask layer 14 is, for instance, an insulation material such as silicon nitride, silicon carbide, or silicon carbon nitride. The mask layer 14 is formed by performing, for instance, a chemical vapor deposition process. Then, the mask layer 14, the liner layer 12, and the substrate 10 are patterned to form a plurality of trenches T in the substrate 10. The patterning method includes, for instance, lithography and etching techniques. Then, an insulation material layer 16 is filled in the trenches T. The material of the insulation material layer 16 is, for instance, silicon oxide. Then, using the patterned mask layer 14 as an etch-stop layer, a chemical mechanical polishing process is performed on the substrate 10 to remove the insulation material layer 16 outside the trenches T.
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The method for forming the protective layer 32 is exemplary and is not intended to limit the invention. In another embodiment, when the second dielectric layer 24 is formed, the thickness of the protective layer 32 is also increased due to high-temperature oxidation, and the protective layer 32 is completely oxidized to form a dielectric layer. In this way, the thickness of the protective layer 32 after the second dielectric layer 24 is formed is greater than the thickness of the protective layer 32 before the second dielectric layer 24 is formed. For instance, the thickness of the protective layer 32 after the second dielectric layer 24 is formed is 1.3 times to 1.5 times the thickness of the protective layer 32 before the second dielectric layer 24 is formed.
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It should be mentioned that, since each of the isolation structures 18 has a protective layer 32, when the second dielectric layer 24 is removed, the protective layer 32 can prevent a portion of the isolation structures 18 adjacent to the surface of the substrate 10 from being removed together. Moreover, since the protective layer 32 is located on a sidewall of the exposed portion 18a of the isolation structures 18, the phenomenon of side etching to the isolation structures 18 caused by the etchant can further be prevented, and therefore the generation of a divot in the periphery of a top corner of the active area 11 is prevented.
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A method for fabricating the semiconductor device 100 includes forming three dielectric layers having different thicknesses, that is, the first dielectric layer 22, the second dielectric layer 24, and the third dielectric layer 26. However, the number is exemplary, and is not intended to limit the invention. In other embodiments of the invention, the method for fabricating the semiconductor device 100 can include forming two, four, or a plurality of dielectric layers having different thicknesses. For instance, the method for fabricating the semiconductor device 100 can further include forming a fourth dielectric layer 28 as described in the following steps.
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It should be mentioned that, since each of the isolation structures 18 has a protective layer 32, when the first dielectric layer 22, the second dielectric layer 24, and the third dielectric layer 26 are removed from the active area 11 of the third region 110 of the peripheral region 104, the removal of the isolation structures 18 adjacent to the periphery of a top corner of the active area 11 at the same time can be prevented, and therefore the generation of a divot is prevented. In other words, the protective layer 32 can prevent the generation of a large divot region as the number of times that different dielectric layers in the periphery of a top corner of the active area 11 are removed is increased, and therefore the generation of electrical issues of the device is prevented.
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A subsequent process for fabricating the semiconductor device 100 includes forming a conductor layer (not shown) on the substrate 10, and after patterning, respectively forming different gate structures on the memory cell region 102 and the peripheral region 104, and thereby respectively forming a needed device such as a memory cell, a select transistor, or a capacitor on the memory cell region 102, the first region 106, the second region 108, and the third region 110. The subsequent process for completing the devices of each of the regions should be known to those skilled in the art, and is not repeated herein.
In the method for fabricating a semiconductor device of the invention, after a tunneling dielectric layer (such as the first dielectric layer 22) of the memory cell is formed and before a thickest gate dielectric layer (such as the second dielectric layer 24) in the peripheral circuit region is formed, by disposing a protective layer on a sidewall of an isolation structure, a divot of the isolation structure formed in the periphery of a top corner of an active area caused by the subsequent repeated removal of gate dielectric layers (gate dielectric layer of a medium-voltage device, gate dielectric layer of an input/output transistor, or gate dielectric layer of a core transistor) of the peripheral circuit region can be prevented. As a result, leakage current of a device can be prevented, and therefore the reliability of the device is increased.
Based on the above, in the method for fabricating a semiconductor device of the invention, by disposing a protective layer on a sidewall of an isolation structure, the protective layer can prevent the isolation structure adjacent to the periphery of a top corner of an active area from being removed when a dielectric layer on the active area is removed, and therefore the generation of a divot in the periphery of a top corner of the active area is prevented. Moreover, when the number of times that dielectric layers on the same active area are removed is increased, the protective layer can also prevent the generation of a large divot region. Moreover, since the protective layer is located on a sidewall of the isolation structure protruding beyond the surface of the substrate, side etching to the isolation structure caused by an etchant can be prevented, and therefore the generation of a divot in the periphery of a top corner of the active area is prevented. As a result, electrical issues such as leakage current of a device are prevented, and therefore the reliability of the device is increased.
Although the invention has been described with reference to the above embodiments, it will be apparent to one of the ordinary skill in the art that modifications to the described embodiments may be made without departing from the spirit of the invention. Accordingly, the scope of the invention is defined by the attached claims not by the above detailed descriptions.
Number | Date | Country | Kind |
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103135650 | Oct 2014 | TW | national |